• Title: Flexible and Efficient QoS Provisioning in AXI4-Based Network-on-Chip Architecture
• Time: 2022
• Journal: TCAD
• Institute: KTH Royal Swedish Institute of Technology

1 Abbreviation

• TDM: Time-Division Multiplexing
• NI: Network Interface
• VC: Virtual Channel

2 References

2 Introduction

Main contributions of this paper:

1. The data conversion between the AXI4 signal format and the NoC packet format is designed in NI, making the NoC design independent of the AXI4 protocol.
2. We defined three different QoS services and designed a network-on-chip based communication architecture
3. We propose a traffic converter unit in each NI to intelligently distribute packets from one heavily congested subnet to another less congested subnet, thereby improving NoC performance.
4. We propose three different flow control mechanisms in the VC subnet and compare their performance results in terms of packet delay in the experimental section.
5. We build a cycle-accurate simulator to simulate the behavior of our proposed system.We present performance evaluation results in terms of system throughput, packet transmission delay, and queuing delay.
6. In the simulator, we propose a two-level Markov Model Process (MMP) based traffic generator to better simulate real processes/threads in nodes.Traffic generation results are reported in our experiments.

3 Background

Industrial Designs for AXI4-Based QoS Of course, none of these components have detailed architectural details

• Xilinx: Control priority based on AXI QoS signaling
• Synopsys: There are QoS regulator and QoS arbiter. If the traffic rate is greater than the expected rate, the QoS regulator can limit the traffic, and the QoS arbiter will serve high-priority requests first
• Intel / Altera: end-to-end flow controller, arbiter, bandwidth regulator

AXI4 ordering
The AXI message request occurs on the master node and the slave node. Due to the out-of-order transmission of NoC, an ordering unit is required on the master side and the slave side, so that the router, switch and traffic converterNo need to worry about ordering; of course, to avoid deadlock problems
QoS requests

• Latency Critical Service (LCS): Similar to CPU, it needs to guarantee low-latency transmission, but does not need to guarantee bandwidth
• Guaranteed Rate Service (GRS): similar to GPU, can tolerate latency, but guarantee bandwidth
• Unspecified Rate Service (URS): Similar to SATA and USB, does not guarantee bandwidth and latency, just transmits data as much as possible

4 System Design

**Message Format Conversion: ** There are two ways of thinking

1. AXI has 5 channels, then I also set 5 channels in NoC, of ​​course, the utilization rate will be very low
2. Convert AXI signals into read requests, response packets, write requests, etc., and transmit them by shared NoC resources

So NI features include

• Accept and process AXI channels and NoC signals
• Convert data format from AXI to NoC packet
• The NI on the slave side inherits the QoS of the requested packet to the corresponding packet, so that the QoS scheme can be transmitted back and forth