1.delay analysis

Static timing analysis (STA) must obtain cell delay and net delay.

• The backend tool calculates the delay per cell and the delay per line
• Unit delay information is provided by unit library files provided by foundary
• In order to calculate line delay, the tool must know the parasitic resistance and parasitic capacitance
of each line

2. cell delay

The cell delay depends on:

• input transition: The smaller the input transition, the smaller the cell delay
• output load : The smaller the output load, the smaller the cell delay
• PVT
  The PVT angle refers to the conditions under which the STA executes.The most common PVT angles are:
• WCS (Slow Process, Low Voltage, High Temperature)
• BCF(Fast Process, High Voltage, Low Temperature)
• Typical(Typical Process, Standard Voltage, Standard Temperature)
• WCL (worst case at low temperature: slow process, low voltage, low temperature)

The generally seen cell delays are all positive values. Actually, the cell delay has negative delays. When the output transition is fast enough, it is entirely possible that the output 50% level is ahead of the input50.% level, that is, a negative delay occurs.

A negative cell delay occurs as follows:

• Driver is powerful enough
• Input transition is small enough
• Output load is small
  

3.net delay

The calculation of the net delay is often carried out by dividing the net in the entire design into several segments, and at the same time, each segment of the net is represented by a certain RC model.
The database after PR tool wiring needs to use Start-RC to extract RC and output it as an RC file in SPEF format.Finally, read the RC file in the Timing signoff tool PT to calculate the delay.
In simple terms:
net delay =~ 3*R*C
So the larger the R*C, the larger the net delay.

Can net delay be negative?
The answer is Yes, in the absence of crosstalk, the net delay must be positive.
If exists crosstalk, when Net1 has a rising edge transition, Net2 also transitions from 0 to 1, and when the transition changes faster than Net1, there will be a negativecrosstalk.It is precisely because of this negative crosstalk that the transition of NET1 is better, resulting in a negative net delay value.