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Verilog HDL Bits training 09 grammar foundation
2022-08-08 13:33:00 【Students with poor south post grades】
文章目录
Circuits:Karnaugh Map to Circuit
一、3-variable

This section talks about the expression obtained through Karnaugh map simplification
This question is simplified
- RTL代码
module top_module(
input a,
input b,
input c,
output out );
assign out = ~(~a & ~b & ~c);
endmodule
- 仿真波形图

二、4-variable

Karnaugh map simplification result is 
- RTL代码
module top_module(
input a,
input b,
input c,
input d,
output out );
assign out = ( ~a & ~b & ~c) | (a & ~b & ~c) | (~a & ~d) | (b & c & d) | (a & ~b & d);
endmodule
- 仿真波形图

三、4-variable

Karnaugh map reduces to(Pay attention to the numbers on the outer row,有陷阱)
- RTL代码
module top_module(
input a,
input b,
input c,
input d,
output out );
assign out = a | (~b & c);
endmodule
- 仿真波形图

四、4-variable

- RTL代码
module top_module(
input a,
input b,
input c,
input d,
output out );
assign out = (~a&~b&~c&d)|(~a&b&~c&~d)|(a&b&~c&d)|(a&~b&~c&~d)|(~a&b&c&d)|(a&~b&c&d)|(~a&~b&c&~d)|(a&b&c&~d);
endmodule
- 仿真波形图

五、Minimum SOP and POS

SOP是以1The center circle is the Carnot circle,POS是以0The center circle is the Carnot circle,Both use the same Karnaugh map.
- RTL代码
module top_module (
input a,
input b,
input c,
input d,
output out_sop,
output out_pos
);
assign out_sop = (c & d) | (~a & ~b &c);
assign out_pos = c & (~b | d) & (~a | d);
endmodule
六、Karnaugh map

- RTL代码
module top_module (
input [4:1] x,
output f );
assign f = (x[2] & x[4]) | (x[3] & x[4]) | (~x[1] & x[3]);
endmodule
七、Karnaugh map

- RTL代码
module top_module (
input [4:1] x,
output f
);
assign f = (~x[2] & ~x[4]) | (~x[1] & x[3]) | (x[2] & x[3] & x[4]);
endmodule
八、K-map implemented with a multiplexer

- RTL代码
module top_module (
input c,
input d,
output [3:0] mux_in
);
assign mux_in[0] = c | d;
assign mux_in[1] = 1'b0;
assign mux_in[2] = ~d;
assign mux_in[3] = c & d;
endmodule
- 仿真波形图

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