一、为什么要用BCD码

FPGAThere is no divider in the resource,when using divisionFPGALogical units are used(LE)中的查找表(LUT)Go build the divider.If it is a remainder of a large number、取整,It will take up a lot of logical resources,Then lead to a certain path delay.
造成的影响:
①时序问题.系统时钟周期20nsNo results can be given within,频率无法达到50M,This leads to problems with the following series of data.
②资源问题.Takes up a lot of logical resources.

因此可以使用BCD码,Use speed for area
流水线,Convert speed to area

二、BCDcode implementation

Used to separate the individual digits of a decimal number,这种称为 移位加3算法 的算法 Only add, subtract and shift operations are used,It can meet the requirements of code portability,The flow of the shift plus three algorithm is as follows（It is assumed here that only 3 个数位）：

1、Shift a binary number left by oneBCD数（未满 4 fill in front 0）
2、如果移动了 8 位,Then the binary numbers are there 百位、十位和个位列,计算结束
3、在任何一个 BCD 列中,if any binary number 大于或者等于 5,就把这个数 加上 3
4、回到步骤 1

三、代码实现

module binary2bcd#(parameter DIN_W = 32,DOUT_W = 40) (
    input                   clk         ,
    input                   rst_n       ,
    input                   en          ,
    input      [DIN_W-1:0]  binary_din  , //输入二进制数据

    output reg [DOUT_W-1:0] bcd_dout    , //输出BCD码数据
    output reg              bcd_dout_vld            
);

//状态机参数定义
    localparam  IDLE  = 4'b0001,
                READY = 4'b0010,
                SHIFT = 4'b0100,
                DONE  = 4'b1000;

//信号定义
    reg     [3:0]           state_c         ;
    reg     [3:0]           state_n         ;

    reg     [DIN_W-1:0]     din_r           ;  //数据锁存

    reg     [5:0]           shift_cnt       ;  //移位次数计数器
    wire                    add_shift_cnt   ;
    wire                    end_shift_cnt   ;

    reg     [3:0]           mem_r0          ;
    reg     [3:0]           mem_r1          ;
    reg     [3:0]           mem_r2          ;
    reg     [3:0]           mem_r3          ;
    reg     [3:0]           mem_r4          ;
    reg     [3:0]           mem_r5          ;
    reg     [3:0]           mem_r6          ;
    reg     [3:0]           mem_r7          ;
    reg     [3:0]           mem_r8          ;
    reg     [3:0]           mem_r9          ;

    wire    [3:0]           mem_w0          ;
    wire    [3:0]           mem_w1          ;
    wire    [3:0]           mem_w2          ;
    wire    [3:0]           mem_w3          ;
    wire    [3:0]           mem_w4          ;
    wire    [3:0]           mem_w5          ;
    wire    [3:0]           mem_w6          ;
    wire    [3:0]           mem_w7          ;
    wire    [3:0]           mem_w8          ;
    wire    [3:0]           mem_w9          ;

    wire    [39:0]          bcd_res         ;

    wire                    idle2ready      ;
    wire                    shift2done      ;

    always @(posedge clk or negedge rst_n) begin
        if(!rst_n)begin
            state_c <= IDLE    ;
        end
        else begin
            state_c <= state_n ;
        end
    end

    always @(*) begin
        case (state_c)
            IDLE :begin
                if(idle2ready)
                    state_n = READY  ;
                else
                    state_n = state_c;
            end
            READY:begin
                state_n = SHIFT;
            end
            SHIFT:begin
                if(shift2done)
                    state_n = DONE   ;
                else
                    state_n = state_c;
            end
            DONE :begin
                state_n = IDLE;
            end 
            default:state_n = IDLE; 
        endcase
    end

    assign idle2ready = state_c == IDLE  && (en) ;
    assign shift2done = state_c == SHIFT && (end_shift_cnt);

    always @(posedge clk or negedge rst_n) begin
        if(!rst_n)begin
            shift_cnt <= 1'd0;
        end
        else if(add_shift_cnt)begin
            if(end_shift_cnt)begin
                shift_cnt <= 1'd0;
            end
            else begin
                shift_cnt <= shift_cnt + 1'd1;
            end
        end
    end
    assign add_shift_cnt = state_c == SHIFT;
    assign end_shift_cnt = add_shift_cnt && shift_cnt == DIN_W - 1 ;

//din_r
    always @(posedge clk or negedge rst_n) begin
        if(!rst_n)begin
            din_r <= 1'b0;
        end
        else if(en)begin
            din_r <= binary_din;
        end
        else if(state_c == SHIFT)begin  //移位状态下,Shift left one bit per clock cycle
            din_r <= din_r << 1'b1;
        end
    end

    always @(posedge clk or negedge rst_n) begin
        if(!rst_n)begin
            mem_r0 <= 0;
            mem_r1 <= 0;
            mem_r2 <= 0;
            mem_r3 <= 0;
            mem_r4 <= 0;
            mem_r5 <= 0;
            mem_r6 <= 0;
            mem_r7 <= 0;
            mem_r8 <= 0;
            mem_r9 <= 0;
        end
        else if(idle2ready)begin
            mem_r0 <= 0;
            mem_r1 <= 0;
            mem_r2 <= 0;
            mem_r3 <= 0;
            mem_r4 <= 0;
            mem_r5 <= 0;
            mem_r6 <= 0;
            mem_r7 <= 0;
            mem_r8 <= 0;
            mem_r9 <= 0;
        end
        else if(state_c == SHIFT)begin
            mem_r0 <= {
    mem_w0[2:0],din_r[DIN_W-1]};
            mem_r1 <= {
    mem_w1[2:0],mem_w0[3]};
            mem_r2 <= {
    mem_w2[2:0],mem_w1[3]};
            mem_r3 <= {
    mem_w3[2:0],mem_w2[3]};
            mem_r4 <= {
    mem_w4[2:0],mem_w3[3]};
            mem_r5 <= {
    mem_w5[2:0],mem_w4[3]};
            mem_r6 <= {
    mem_w6[2:0],mem_w5[3]};
            mem_r7 <= {
    mem_w7[2:0],mem_w6[3]};
            mem_r8 <= {
    mem_w8[2:0],mem_w7[3]};
            mem_r9 <= {
    mem_w9[2:0],mem_w8[3]};
        end
    end

    assign mem_w0 = (mem_r0 > 4'd4)?(mem_r0 + 4'd3):mem_r0;
    assign mem_w1 = (mem_r1 > 4'd4)?(mem_r1 + 4'd3):mem_r1;
    assign mem_w2 = (mem_r2 > 4'd4)?(mem_r2 + 4'd3):mem_r2;
    assign mem_w3 = (mem_r3 > 4'd4)?(mem_r3 + 4'd3):mem_r3;
    assign mem_w4 = (mem_r4 > 4'd4)?(mem_r4 + 4'd3):mem_r4;
    assign mem_w5 = (mem_r5 > 4'd4)?(mem_r5 + 4'd3):mem_r5;
    assign mem_w6 = (mem_r6 > 4'd4)?(mem_r6 + 4'd3):mem_r6;
    assign mem_w7 = (mem_r7 > 4'd4)?(mem_r7 + 4'd3):mem_r7;
    assign mem_w8 = (mem_r8 > 4'd4)?(mem_r8 + 4'd3):mem_r8;
    assign mem_w9 = (mem_r9 > 4'd4)?(mem_r9 + 4'd3):mem_r9;

    assign bcd_res = {
    mem_r9,mem_r8,mem_r7,mem_r6,mem_r5,mem_r4,mem_r3,mem_r2,mem_r1,mem_r0};

    always @(posedge clk or negedge rst_n) begin
        if(!rst_n)begin
            bcd_dout <= 1'b0;
        end
        else if(state_c == DONE)begin
            bcd_dout <= bcd_res[DOUT_W-1:0];
        end
    end

    always @(posedge clk or negedge rst_n) begin
        if(!rst_n)begin
            bcd_dout_vld <= 1'b0;
        end
        else begin
            bcd_dout_vld <= state_c == DONE;
        end
    end


endmodule