FPGA SEU problem and SEM core

Xilinx The design of the SEM Core

Fortunately, , because SEU The probability of occurrence of this phenomenon is extremely low , Most common design applications do not need to consider this problem . But in aviation 、 Aerospace and other high reliability requirements , Or in some high-altitude areas , happen SEU The probability of will increase accordingly . In order to correct this situation in time SEU Throw a function exception , Further improve FPGA Reliability of devices ,Xilinx Developed Soft Error MitigationCore, abbreviation SEM IP.

FPGA The internal storage unit is mainly divided into 4 Categories: ：Configuration RAM （CRAM）, Block RAM (BRAM), Distributed RAM (DRAM) as well as Flip-Flops(FF).CRAM Used to store FPGA Configuration data of , It is also the storage unit module with the largest proportion . The proportion of the remaining three decreased in turn , Can be used by user logic .

SEM IP You can scan continuously FPGA Of CRAM, Quickly detect whether there is any storage unit content inconsistent with the initial value , And the value of the storage unit that has been overturned can be repaired to the original value . The IP Less occupied resources , Easy to use and flexible , Can correct most in time SEU error , This avoids reconfiguration FPGA Trouble .

It should be noted that ,SEM IP The remaining three types of storage units are not scanned .BRAM Although it is also a large number of storage unit modules , but Xilinx Of BRAM You can open your own ECC Check function , correct SEU Or data errors caused by other problems . in addition ,DRAM and FF The number of is relatively small , Superposition consideration SEU Very low probability of occurrence of the phenomenon , These two parts are SEU Problems can generally be safely ignored .