1. AARCH64 Build the compilation environment

git clone https://github.com/tianocore/edk2-platforms.git
git clone https://github.com/acpica/acpica.git
git clone https://github.com/tianocore/edk2.git
 
cd edk2
git submodule update --init
cd ..

sudo apt-get install gcc-aarch64-linux-gnu
sudo apt-get install qemu-system-aarch64

export WORKSPACE=$PWD
export PACKAGES_PATH=$WORKSPACE/edk2:$WORKSPACE/edk2-platforms
export IASL_PREFIX=$WORKSPACE/acpica/generate/unix/bin/
export GCC5_AARCH64_PREFIX=/usr/bin/aarch64-linux-gnu-

source edk2/edksetup.sh
build -a AARCH64 -t GCC5 -p edk2/ArmVirtPkg/ArmVirtQemu.dsc -b DEBUG

After compiling, it will generate UEFI file ：Build/ArmVirtQemu-AARCH64/DEBUG_GCC5/FV/QEMU_EFI.fd

Run the command as follows

 qemu-system-aarch64 -M virt -cpu cortex-a57 -bios Build/ArmVirtQemu-AARCH64/DEBUG_GCC5/FV/QEMU_EFI.fd -net none -serial stdio

2. ArmPlatformPriPeiCore

Most tutorials use OVMF To make the sample ,OVMF The first to run UEFI The module is SEC. but AARCH64 Medium SEC This is it ArmPlatformPriPeiCore. So in edk2 Of AARCH64 Example ,ArmPlatformPriPeiCore Is the first module to run .

2.1 QEMU_EFI.fd What is included

We use it UEFITool NE open QEMU_EFI.fd, You can see the following figure

1. ArmPlatformPrePeiCore, Act as the SEC core Module . from 0x1000 Deposit
2. PeiCore,PEI Core Code for
3. 7 individual PEIM

   PEIM	function
   PlatformPei	initialization SOC Platform related code
   MemoryInit	Initialize memory
   CpuPei	initialization ARM cortex a57 cluster
   PcdPeim	Provide dynamic Pcd
   PeiVariablePei	Not used
   DxeIplPei	Provide load DXE The function of

4. And finally a Volumn image, This is a compressed volume , It contains PEI Later stage image, Such as DXE, BSD wait . Need to be in PEI Unzip and run .

2.2 QEMU virt aarch64 relevant

• ROM The space of is 0x00000000 - 0x3FFFFFFF
• RAM The space is 0x40000000 - 0x7FFFFFFF
• CPU The first instruction is in 0 Address operation , That is to say ROM On
• QEMU_EFI.fd The documents are stored in ROM On , From 0 Address start

2.3 From the first instruction to ArmPlatformPrePeiCore entrance

from 2.2 We know CPU The first instruction is from 0 Address execution , that QEMU_EFI.fd The first one in word Stored something ？ View with binary editor QEMU_EFI.fd You can see in the 0 The address stores a word：0x14000400.

This is a jump command , according to armv8a Look at your manual , This command is b pc+0x1000.CPU When it started ,PC The register is 0, So this command will jump directly to 0x1000 Address .

Then look at the same 0x1000 Address data . Another jump command 0x14000d16. The result is b pc+0x3458, At present pc yes 0x1000, So he jumped to 0x4458.

that 0x4458 What is stored ？
First, through disassembly ArmPlatformPrePeiCore.debug, You can get 0x3458 yes ArmPlatformPrePeiCore Of _ModuleEntryPoint

And then we look at QEMU_EFI.fd Of 0x4458 Data stored at the address of , It's corresponding to _ModuleEntryPoint The first instruction of . We know ArmPlatformPrePeiCore It's from 0x1000 Deposited , So in fact 0x4458 Namely ArmPlatformPrePeiCore Of _ModuleEntryPoint. and ArmPlatformPrePeiCore The compiled code is location independent code , So pass 0 Address and 0x1000 Two jumps of address , Finally jump to ArmPlatformPrePeiCore Of _ModuleEntryPoint in .

2.4 ArmPlatformPrePeiCore Did something

ArmPlatformPrePeiCore It's simple , Primary initialization CPU, Set the stack pointer , initialization PEI Parameters required for the phase SecCoreData Finally jump to PEI core In the middle .

The function call stack is as follows ：

_ModuleEntryPoint
	_SetupPrimaryCoreStack
		_PrepareArguments
			CEntryPoint
				PrimaryMain
					(PeiCoreEntryPoint)(&SecCoreData, PpiList);

_ModuleEntryPoint

edk2/ArmPlatformPkg/PrePeiCore/AArch64/PrePeiCoreEntryPoint.S
This first calls ArmPlatformPeiBootAction, This function is an empty implementation , It doesn't really work . Then call SetupExceptionLevel1 Set up EL1 Environment , And then jump to MainEntryPoint.

ASM_FUNC(_ModuleEntryPoint)
  // Do early platform specific actions
  bl    ASM_PFX(ArmPlatformPeiBootAction)
  
  EL1_OR_EL2(x0)
1:bl    ASM_PFX(SetupExceptionLevel1)
  b     ASM_PFX(MainEntryPoint)

MainEntryPoint Read in CPU ID Configure the stack pointer , If it is primary core Is set primary Stack , If it is secondary core Is set secondary Stack . We'll just talk about primary core. Stack pointer from FIX PCD In order to get

ASM_PFX(MainEntryPoint):
  MOV64 (x1, FixedPcdGet64(PcdCPUCoresStackBase) + FixedPcdGet32(PcdCPUCorePrimaryStackSize))
  // x0 is equal to 1 if I am the primary core
  cmp   x0, #1
  b.eq   _SetupPrimaryCoreStack

_SetupPrimaryCoreStackz Stack registers are mainly configured in SP, And then jump to _PrepareArguments

_SetupPrimaryCoreStack:
  mov   sp, x1
 ...
  b     _PrepareArguments

_PrepareArguments from PCD I'll get PEI CORE Of entry, Then pass it to CEntryPoint, The back is C Code.

_PrepareArguments:
  // The PEI Core Entry Point has been computed by GenFV and stored in the second entry of the Reset Vector
  MOV64 (x2, FixedPcdGet64(PcdFvBaseAddress))
  ldr   x1, [x2, #8]

  // Move sec startup address into a data register
  // Ensure we're jumping to FV version of the code (not boot remapped alias)
  ldr   x3, =ASM_PFX(CEntryPoint)

CEntryPoint

edk2/ArmPlatformPkg/PrePeiCore/PrePeiCore.c
CEntryPoint It mainly initializes some ARM CPU Something about , close cache, open VFP, Set up VBAR And so on. , And then jump to PrimaryMain In the .

CEntryPoint (
  IN  UINTN                     MpId,
  IN  EFI_PEI_CORE_ENTRY_POINT  PeiCoreEntryPoint
  )
{
    
  // Close all Dcache
  ArmDisableDataCache ();
  // Invalid all ICache
  ArmInvalidateInstructionCache ();
  //  Can make ICACHE
  ArmEnableInstructionCache ();
  //  Brush off the stack Dcache
  InvalidateDataCacheRange (
    (VOID *)(UINTN)PcdGet64 (PcdCPUCoresStackBase),
    PcdGet32 (PcdCPUCorePrimaryStackSize)
    );
  // Set up VBAR To PeiVectorTable --> PEI Exception vector table 
  ArmWriteVBar ((UINTN)PeiVectorTable);
  // Enable floating point units 
  ArmEnableVFP ();
  PrimaryMain (PeiCoreEntryPoint);
}

PrimaryMain

edk2/ArmPlatformPkg/PrePeiCore/MainMPCore.c
PrimaryMain It mainly established SEC Phase to phase PEI Of PPI list, And then configure it SecCoreData Structure , Jump to PeiCore In the middle .

VOID
EFIAPI
PrimaryMain (
  IN  EFI_PEI_CORE_ENTRY_POINT  PeiCoreEntryPoint
  )
{
    
  ...
  // establish SEC Stage PPI
  CreatePpiList (&PpiListSize, &PpiList);
  // Can make GIC
  ArmGicEnableDistributor (PcdGet64 (PcdGicDistributorBase));

  ...
  // from PCD In order to get TempStack Of base,TempStack Temporary memory before permanent memory initialization 
  TemporaryRamBase = (UINTN)PcdGet64 (PcdCPUCoresStackBase) + PpiListSize;
  // from PCD In order to get TempStack Size 
  TemporaryRamSize = (UINTN)PcdGet32 (PcdCPUCorePrimaryStackSize) - PpiListSize;

  SecCoreData.DataSize               = sizeof (EFI_SEC_PEI_HAND_OFF);
  // from PCD In order to get PEI Of FV Address and length and store in SecCoreData in 
  SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet64 (PcdFvBaseAddress);
  SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdFvSize);
  
  SecCoreData.TemporaryRamBase       = (VOID *)TemporaryRamBase; // We run on the primary core (and so we use the first stack)
  SecCoreData.TemporaryRamSize       = TemporaryRamSize;
  SecCoreData.PeiTemporaryRamBase    = SecCoreData.TemporaryRamBase;
  SecCoreData.PeiTemporaryRamSize    = ALIGN_VALUE (SecCoreData.TemporaryRamSize / 2, CPU_STACK_ALIGNMENT);
  SecCoreData.StackBase              = (VOID *)((UINTN)SecCoreData.TemporaryRamBase + SecCoreData.PeiTemporaryRamSize);
  SecCoreData.StackSize              = (TemporaryRamBase + TemporaryRamSize) - (UINTN)SecCoreData.StackBase;

  // Jump to PEI core entry point
  PeiCoreEntryPoint (&SecCoreData, PpiList);
}

We are PeiCore The entrance of the has been added with printing , hold SecCoreData dump Come out as follows

DataSize:48
BootFirmwareVolumeBase:00000001000
BootFirmwareVolumeSize:000001FF000
TemporaryRamBase:0004007C030
TemporaryRamSize:00000003FD0
PeiTemporaryRamBase:0004007C030
PeiTemporaryRamSize:00000001FF0
StackBase:0004007E020
StackSize:00000001FE0

thus ,SEC It's over , The back is PEI The execution of the phase