Why Latches should be avoided in digital IC design

When I was in school, the teacher said that the judgment statement should write all the conditions, otherwise a latch would be generated. When working on the project, he said that the assignment of multi-bit register signals must add an if condition to prevent the assignment of else.It is very contradictory. This article mainly talks about what a latch is, under what circumstances a latch occurs, and the harm of a latch

I. What is a latch?

Latch is a memory cell circuit that is sensitive to pulse level, and they can change state under the action of a specific input pulse level [1].In other words, if a module's input information will be updated to its output pins only under the action of a specific level, otherwise the output of the module will remain unchanged, then this module can be regarded as aLatches.

The structure of a common S-R register is as follows:

The truth table is

When S and R are 00, the output Q can be kept unchanged, so as to achieve the purpose of using combinational logic to achieve storage;

Second, under what circumstances does a latch appear?

Sequential logic does not require latches to store data due to the existence of registers; while the conditions of combinational logic are not given full time, a latch will appear;

For example

[email protected](*)if(vld)a = b;

At this time, since there is no case where vld is 0, it will not be instantiated as a selector of two alternatives, but a latch will be instantiated to achieve the storage function of keeping data unchanged when vld is 0;

Third, why should latches be avoided?

Latches have the following disadvantages:

• Cannot be reset asynchronously and is in an indeterminate state after power up.
• Latches can complicate static timing analysis;
• If the circuit is built on an FPGA, since the basic unit in the FPGA is composed of a look-up table and flip-flops, more resources are needed to generate latches;
• Latches are sensitive to glitches and will cause circuit instability (I don't understand this, can instantiating a selector solve this problem??)

References

【1】 Latch_360 Encyclopedia (so.com)
【2] CSDN: Causes, Harm and Avoidance of Latch in FPGA Learninghref="https://blog.csdn.net/kuan__/article/details/124392567?ops_request_misc=%257B%2522request%255Fid%2522%253A%2522165959877816782248522021%2522%252C%2522scm%2522%253A%252220140713.130102334.pc%255Fall.%2522%257D&request_id=165959877816782248522021&biz_id=0&utm_medium=distribute.pc_search_result.none-task-blog-2~all~first_rank_ecpm_v1~pc_rank_34-9-124392567-null-null.142%5Ev39%5Epc_rank_34_queryrelevant0&utm_term=%E9%94%81%E5%AD%98%E5%99%A8%E5%AF%84%E5%AD%98%E5%99%A8&spm=1018.2226.3001.4187">CSDN: The relationship and difference between latches, D flip-flops and registers