Bare metal configuration hardware SPI

The details of the SPI For the introduction of timing, please see my other article ：STM32 And SPI Detailed analysis

ESPI Introduce

IMX6U Self contained SPI The peripheral is called ECSPI, The full name is Enhanced Configurable Serial Peripheral Interface,ECSPI Contains a 64x32 Receive buffer (RXFIFO) And a 64x32 Transfer buffer (TXFIFO). By data FIFOs,ECSPI Allows fast data communication with fewer software interruptions .IMX6U Yes 4 individual ESPI. The picture below is ECSPI Diagram of . By a stack of registers , Clock generator , External pins , A state machine consists of .

Characteristics are as follows ：
① Full duplex synchronous serial interface .
② Configurable master / Slave mode .
③ Four chip selection signals , Support multiple slaves .
④ Both sending and receiving have a 32x64 Of FIFO.
⑤ Piece of optional signal SS/CS, Clock signal SCLK Polarity configurable .
⑥ Support DMA.

Supported modes are 3 Kind of ：
① Host mode
② Slave mode
③ Low power mode

External pins

And usual SPI equally , There are MOSI、MISO、CLK、CS Pin , however ESPI Hardware chip selection pin support 4 Select an external device .（ Software configuration pins can be used instead of hardware chip selection pins .）

The clock

ESPI The clock sources are 4 An option ：

register

Each group SPI All have the following register groups . Include ： Data receiving register 、 Data transmission register 、 Control register 、 Configuration register 、 Interrupt register 、DMA register 、 Status register 、 Sampling period control register 、 Test the control register 、 Message data register .

ECSPIx_RXDATA： Data receiving register ; because ECSPI The data receiving block of is a 64*32 Of FIFO block , Therefore, the data receiving register is used as the header in this block .

ECSPIx_TXDATA： Data transmission register ; Empathy ECSPIx_RXDATA, It is the header of the data transmission block .

ECSPIx_CONREG： Control register , To enable SPI, Configure working mode, etc .

[ Failed to transfer the external chain picture , The origin station may have anti-theft chain mechanism , It is suggested to save the pictures and upload them directly (img-1vEIRyDW-1650546158115)(C:\Users\15894\AppData\Roaming\Typora\typora-user-images\image-20220421201406035.png)]

• BURST_LENGTH paragraph ： Burst length , I.e. configuration SPI Burst transmission data length , Up to 2^12bit, The general configuration is 8bit
• CHANNEL_SELECT paragraph ：SPI Channel selection
• DRCTL paragraph ： Configure the preparation signal .0： No concern ,1： edge-triggered ,2： Level trigger
• PRE_DIVIDER paragraph ： To configure SPI Clock prescaler
• POST_DIVIDER paragraph ： To configure SPI The clock frequency division
• CHANNEL_MODE：SPI On off mode selection ,1： Main mode ,0： Slave mode
• SMC： Start mode control
• XCH： Configure whether to turn on SPI Burst access
• EN：SPI Enable bit ,1 Can make ,0 close

ECSPIx_CONFIGREG： Configuration register , To configure SPI Some related parameters

• SCLK_CTL： To configure SCLK Idle state level of the signal ,4 bits , They correspond to each other 4 Channels ,0： Low level ,1： High level

• DATA_CTL： Configure the idle state level of the data line ,4 bits , They correspond to each other 4 Channels ,0： Low level ,1： High level

• SS_POL： Configure chip selection signal polarity ,4 bits , They correspond to each other 4 Channels ,0： Low level active ,1： High active

• SCLK_POL： To configure SPI Clock polarity

• SCLK_PHA： To configure SPI Clock phase

ECSPIx_INTREG： Interrupt control register , Altogether 8 A break

ECSPIx_DMAREG：DMA Control register

ECSPIx_STATREG： Status register , Defined 8 States , There were ： Transmission complete 、RXFIFO overflow 、RXFIFO empty 、RXFIFO Data request 、RXFIFO be ready 、TXFIFO full 、TXFIFO Data request 、TXFIFO empty .

ECSPIx_PERIODREG： Sampling period control register

SPI Primary communication flow in host mode

1. To configure CONREG and CONFIGREG register
2. Configure interrupt register （ Optional ）
3. To configure DMA register （ Optional ）
4. To configure SPI The clock （ Optional ）
5. choice SPI passageway
6. Waiting to send FIFO It's empty
7. Fill the sending block （ namely TXFIFO）
8. Waiting to receive FIFO There's data
9. Transfer the data in the receiving block

The code analysis

C file

#include "bsp_spi.h"
#include "bsp_gpio.h"
#include "stdio.h"

/*  initialization SPI */
void spi_init(ECSPI_Type *base)
{
    
	/*  To configure CONREG register  * bit0 : 1  Can make ECSPI * bit3 : 1  Direction TXFIFO Turn on immediately after writing data SPI Sudden . * bit[7:4] : 0001 SPI passageway 0 Main mode , Choose... According to the actual situation , * bit[19:18]: 00  Select the channel 0 * bit[31:20]: 0x7  The burst length is 8 individual bit. */
	base->CONREG = 0; /*  Clear the control register first  */
	base->CONREG |= (1 << 0) | (1 << 3) | (1 << 4) | (7 << 20); /*  To configure CONREG register  */

	base->CONFIGREG = 0; 		/*  Set the channel register  */
	
	/* ECSPI passageway 0 Set up , Set the sampling period , That is, the interval between each time when reading data  */
	base->PERIODREG = 0X2000;		  /*  Set the sampling period register  */

	/* * ECSPI Of SPI Clock configuration ,SPI The source of the clock comes from pll3_sw_clk/8=480/8=60MHz *  By setting CONREG The register of PER_DIVIDER(bit[11:8]) and POST_DIVEDER(bit[15:12]) Come on  *  Yes SPI Clock source frequency division , Get what we want SPI The clock ： * SPI CLK = (SourceCLK / PER_DIVIDER) / (2^POST_DIVEDER) *  For example, we are now going to set SPI The clock is 6MHz, that PER_DIVEIDER and POST_DEIVIDER Set as follows ： * PER_DIVIDER = 0X9. * POST_DIVIDER = 0X0. * SPI CLK = 60000000/(0X9 + 1) = 60000000=6MHz */
	base->CONREG &= ~((0XF << 12) | (0XF << 8)); /*  eliminate PER_DIVDER and POST_DIVEDER */
	base->CONREG |= (0X9 << 12);				 /*  Set up SPI CLK = 6MHz */
}

/* SPI passageway 0 send out / Receive one byte of data  */
unsigned char  spi_transmit_byte(ECSPI_Type *base, unsigned char txdata)
{
     
	uint32_t  spirxdata = 0;
	uint32_t  spitxdata = txdata;
    /*  Select the channel 0 */
	base->CONREG &= ~(3 << 18);
	base->CONREG |= (0 << 18);
  	while((base->STATREG & (1 << 0)) == 0){
    } 	/*  Waiting to send FIFO It's empty  */
		base->TXDATA = spitxdata;
	while((base->STATREG & (1 << 3)) == 0){
    } 	/*  Waiting to receive FIFO There's data  */
		spirxdata = base->RXDATA;
	return spirxdata;
}

H file

#ifndef _BSP_SPI_H
#define _BSP_SPI_H

#include "imx6ul.h"

/*  Function declaration  */
void spi_init(ECSPI_Type *base);
unsigned char spi_transmit_byte(ECSPI_Type *base, unsigned char txdata);

#endif