Quartus II prevents signals from being integrated

In some applications , There are certain signals that we need to keep , Used for acquisition and detection , And the synthesizer will automatically optimize and integrate it , that , How to tell the synthesizer , Don't let it optimize the signals we need to keep ？

The treatment of this situation is to add constraints , share 2 In this case ：

1、 The signal that needs to be retained is the lead
Verilog HDL— When defining, add /* synthesis keep */.
for example ：wire keep_wire /* synthesis keep */;

2、 You need to keep the yes register

Follow reg dependent synthesis attribute, There are two kinds of , Namely /*synthesis noprune*/ and /*synthesis preserve*/, The differences between the two are as follows ：

/*synthesis noprune*/ avoid Quartus II Optimized output Of reg.

/*synthesis preserve*/ avoid Quartus II Will reg Optimize to constant , Or merge duplicate reg.

When defining, add relevant constraint statements later .
for example ：reg reg1 /* synthesis noprune*/; perhaps reg reg1 /* synthesis preserve */;

Will /*synthesis noprune*/ etc. synthesis attribute Put the sentence in module Back , So the whole module Of reg Will not be optimized , Thus, there is no need to specify... In another register .
 

Be careful ： As mentioned above synthesis attribute Must be written before the closing semicolon , Writing after a semicolon is only equivalent to a comment ：

correct ：reg reg1 /* synthesis preserve */;

error ：reg reg1 ;/* synthesis preserve */

The above articles are from the network and handbook Sum up , Welcome to reprint .

reference ：

( Original ) How to use SignalTap II Observation reg And wire value ? (SOC) (Verilog) (Quartus II) (SignalTap II) http://www.cnblogs.com/oomusou/archive/2008/10/17/signaltap_ii_reg_wire.html

quartus How to keep the signal from being integrated in  http://wenku.baidu.com/link?url=OcL9wZlxGCcVfnEHGD9FpCKkCmN3P9uYoK1TkLh6gGGGZs6Ip589f_v-d64V1CCtlnR2rrB6GRS01BDVhnWmrqHH2ScEiel6Rzayh1G-IfG