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Overview of the paper

   The title of this paper is Automated Generation of RAL-based UVM Sequences, The author is Intel Canadian Engineers .

   This paper puts forward a kind of be based on RAL（ Register abstraction layer ） Of UVM Sequence Automatic generation Method , And discussed it. By dividing TB Constrain the range to speed up the simulation The problem of .

research objective

   generally , We control by configuring a set of registers DUT The hardware behavior of , In order to make DUT Work in a certain feature Next . For different feature, The configured registers and the order of the configured registers may be different . at present , The common method of configuring registers is to use UVM RAL Model To configure the DUT register . That means ： We need to target every feature Draw up a programming sequence, and coding become uvm sequence.

   I think everyone DV Students have encountered these situations in the verification process ：feature That's too much ,feature It has changed again ,programming sequence It has changed again , The register has changed again …… Write manually 、 Manual modification , My hands are numb , It makes people swear .

   What do I do ？ automation ！ Automate with scripts ！

The new method

   This paper puts forward a kind of Automatic generation from design documents based on RAL Of UVM Sequence Methods , And discussed it. By dividing TB Constrain the range to speed up the simulation The problem of . chart 1 It's script generation UVM sequence Of UVM The test framework .

chart 1 Modified UVM test framework integrated with the RAL and UVM sequence auto-generation scripts

   The main idea of this method is summarized as follows ：

1. Standard design documents . Write a design in a specific format spec, Machine readable is required . This document needs to contain two important sub documents spec, One is the register spec, The second is each feature Of programming sequence spec.
2. Parsing script . Automatically parse the document with a script , Automatic generation uvm sequence and ral sequence.
3. Every time the design document is updated , Re parse and regenerate the related data sequence that will do .

   In the above methods , There are a few places I would like to focus on ：

1. In design documents programming sequence It is designed as a state machine form of directed acyclic graph , It is convenient for the script to correctly generate the corresponding uvm sequence.
2. In order to improve the coverage, It needs to be right RAL Model The register values of are random in a large range . In larger designs , But considering that there may be dependencies between registers , Only by ral At random or manually ral It is unrealistic to add random constraints in ,ral model Random constraints on all registers are complex , It takes a long time to break the contract . And it's different feature Next ral model The random scheme is also different . In this automatic generation environment , How to achieve it ?—— For use config_db, every last feature Of test Of uvm sequence All correspond to a specific config_db, stay test in set to ral sequence, And only randomly what we're verifying block Related registers , So as to reduce the time of solving the random constraint （ It's the accelerated simulation mentioned earlier ）, It can also prevent random unexpected wrong results .

Discuss

   This method is good ,DV No longer afraid of changes in design documents ！

   The method is a good one , But to tell you the truth, , The automatic generation used in this paper test sequence The concept of is not very new , Mature companies have similar scripts .

   Really use this method , need DE Students are writing design spec Be more standard when you . In especial programming sequence, How to configure each register 、 How much , Write clearly . So much feature …… This method The liberation of the DV, bitter DE ah , It is estimated that DE I'm going to curse my mother .DE Don't write DV You can write if you like , If no one writes , This method doesn't work .

End

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