1. many bit sign Sampling intermediate state ——Gray code

How much is this bit New problems specific to signals , First in asynchronous FIFO When reading and writing the pointer across the clock domain, it is found .

Because there are many bit Binary change , So it's probably due to Clock skew , The clock edge does not reach each trigger at the same time , Cause those bit The changes of bits are not simultaneous

Therefore, the asynchronous clock is likely to sample the intermediate state of the jump process

For example, two triggers from 01 Jumping 10, Due to the clock skew, the first bit posedge clk Come first 、 Second posedge clk After the , So the first trigger D End to end 1 Good morning! 、 The second trigger D End to end 0 On the evening of , So there is an intermediate state 11 May be sampled by asynchronous clock to .
So if the number of bits of the signal is more , So there will be a lot of intermediate states

Note that the essence of this problem is that each clock cycle involves the level change of multiple flip flops , So can we Reduce each clock edge Number of triggers for level change ？

The third value will not appear in the process of numerical change Gray code that will do

for example Gray Code signal from 01 become 11, There will be no intermediate value . Or sample to the old value 01, Or it's a new value 11

2. many bit Data signals

This is asynchronous FIFO All right , Write... At one end 、 One end read , Reading and writing clocks are different .

But asynchrony FIFO In fact, it does not solve the problem of cross clock domain of data signals , Instead, it turns the problem into more bit The cross clock domain problem of reading and writing pointers .

So for the read-write pointer , Level synchronization required + Grey Code processing , At the same time, read-write logic does not pay attention to the change process of read-write pointer , Therefore, the multi sampling problem of fast mining and slow mining and the leakage problem of slow mining and fast mining will not have an impact .

therefore ,full and empty Signs do not reflect the current moment in real time FIFO The true state of , But this error does not cause full write and empty read problems .

For details, see asynchronous FIFO Design