register

Base address

about MCMCAN modular , All registers are prefixed with CAN0_、CAN1_ or CAN2_, Specific product variants may have corresponding modules .
The register is divided into three different parts ：

• General Configuration Registers
• User Interface Registers
• Registers within M_CAN

CAN Clock Control Register（CLC）

Clock control register CLC Allows the programmer to adjust the function and power consumption of the module according to the application requirements . The following description shows the clock control register function implemented in the standard interface of the module . When the module kernel is connected to CLC Clock control interface ,CLC Of the control module f(SYN) and f(ASYN) Module clock signal 、 Sleep mode and quick shutdown mode .

Module Control Register(MCR)

Module control register MCR Include OK MCMCAN Basic settings for module operation . If and only if... Is set during write access MCR.CCCE and MCR.CI when , Yes MCR Write access to the lowest byte of the register is valid . To turn the clock on or off , It must then be reset MCR.CCCE and MCR.CI Bit . Before this sequence happens , No write access to the corresponding node .
In order to be able to change the clock settings , The following programming sequence needs to be met ：

uwTemp = CANn_MCR.U;
uwTemp |= (0xC0000000 | CLKSELx);
CANn_MCR.U = uwTemp;
uwTemp &= ~0xC0000000;
CANn_MCR.U = uwTemp;
// The clock settings for CAN nodes becomes active.
// To be able to start the RAM initialization, the following programming sequence need to be met:
CANn_MCR |= 0xC0000000;
// Wait until CANn_MCR.RBUSY is 0b
// Set CANn_MCR.RINIT to 0b
// Set CANn_MCR.RINIT to 1b
// Dummy read CANn_MCR
// Wait until CANn_MCR.RBUSY is 0b
// Set CANn_MCR.RINIT to 0b
CANn_MCR &= ~0xC0000000;
// RAM initialization is finished

CC Control Register i( CCCRi (i=0-3) )

CCCRi Register enable and disable CAN Bus participation and basic protocol functions . Due to the synchronization mechanism between clock domains , In the face of CCCRi Write after operation , The register should be read back , Until the setting value is written to the register . please remember , The register also includes bits affected by hardware .

stay MCR Enable... In register CAN After clock , The application must wait 10 The host core can only access a clock cycle .
LDMST or SWAPMSK.W The instruction can only be used for rwh Use when bit mask is enabled