The fifth bullet of FPGA development: hand rubbing breathing light code

​ The PWM method adopted by the breathing light controls the brightness of the LED light by adjusting the duty cycle at a fixed frequency.PWM stands for Pulse Width Limitation.

​ Under the fixed-period PWM signal generated by the counter, the duty cycle is 0, and the LED is not bright; the duty cycle is 100%, and the LED is the brightest.Changing the duty cycle from 0 to 100, the breathing light effect can be achieved.

​ The schematic diagram of PWM duty cycle adjustment is as follows:

​ The longer the LED is high, the brighter the LED, and the shorter the high time, the darker the LED.

​ The module port and structural block diagram of this experiment are shown in the following figure:

​ The pin assignments of the system clock, key reset and LED port in the experiment are shown in the table below.

​ The corresponding XDC constraint statement is as follows:

create_clock -name clk -period 20 [get_ports clk]set_property -dict {PACKAGE_PIN R4 IOSTANDARD LVCMOS33} [get_ports clk]set_property -dict {PACKAGE_PIN U2 IOSTANDARD LVCMOS33} [get_ports rst]set_property -dict {PACKAGE_PIN R2 IOSTANDARD LVCMOS33} [get_ports led]

​ The breathing light code is as follows:

module breath_led(input clk,input rst,output led);reg[15:0] period;reg[15:0] pwm;reg state;//led changes according to the state of period and pwmassign led=(period>=pwm)?1'b1:1'b0;//Counter, record 50000, 20nsalways @(posedge clk or negedge rst)beginif(rst==0)period<=16'd0;else if(period==16'd50000)period<=16'd0;elseperiod<=period+1'b1;endalways @(posedge clk or negedge rst)//duty cycle setting modulebeginif(rst==0)beginpwm<=16'd0;//Initialize pwm to 0, state to 0state<=1'b0;endelsebeginif(period==16'd50000)//If the counter is fullbeginif(state==1'b0)//If the state is 0beginif(pwm==16'd50000)//If pwm=50000state<=1'b1;//The state is changed to 1else//pwm!=50000pwm<=pwm+16'd25;//pwm changes with 25endelse//If the state is 1beginif(pwm==16'd0)//If pwm=0state<=1'b0;//The state is changed to 0else//pwm!=0pwm<=pwm-16'd25;//pwm gradually decreases by 25endendendendendmodule

​ The core is the comparison between the current cycle count value and the duty cycle. If the current cycle count value is less than or equal to the duty cycle count value, the LED outputs a high level, that is, lights up;If the value is greater than the duty cycle value, the LED output is low, that is, it goes out.

​ Finally, a bitstream is generated for download verification.

​ For specific operation steps, please refer to the first bullet of FPGA development: The first bullet of FPGA development: Vivado software installation, development and useBuilding with the project

​ The above is the breathing light experiment I conducted, and I continue to be familiar with the entire FPGA development process. If you are doing your own project, you can’t miss every step. Every step needs to be summed up and mastered carefully.proficient!Welcome everyone to private message me to exchange and learn together, and welcome everyone to criticize and correct!