一、实验分析

1、实验要求

请用 verilog 写一个模块,The implementation window width is ５moving average filter.Let the filter function be denoted as y=avg(x)

其中输入x为一个长度为Ｎ的８bit 离散序列.输出yAlso for lengthＮ的８bit离散序列.Then the function can be represented by the following pseudocode.(The code can refer to the followingavg.c)

#define N 32 
void avg(unsigned char* x, unsigned char* y) 
{
     
int i, j, k; 
int sum; 
unsigned char avg; 
for (i = 0; i < N; i++) 
{
     
sum = 0; 
for (j = -2; j <= 2; j++) 
{
     
k = i + j; 
if (k >= 0 && k < N) 
sum += x[k]; 
} 
avg = sum * 51 / 256; 
y[i] = avg; 
} 
}

请用 verilog 实现以上函数.

提示：

1. 窗口宽度为５,So doing the average operation and dividing by５时,用 51/256 近似 1/5,to ensure that the test passes.
2. Please use the pipeline structure to achieve.

2、实验设计

结构图如下：

二、项目源码

`timescale 1ns/1ps
/********************************************************** // Copyright 2022.05-2025.05 // Contact with [email protected] ================ xxx.v ====================== >> Author : lzh >> Date : >> Description : 实现滑动平均滤波,滑动窗口为5 >> note : Timing optimization is done,最大能够达到150MHz >> : >> V180121 : ************************************************************/

module fir_test3 (
    input               clk     ,
    input               rst_n   ,
    input               vin     ,   //输入有效信号
    input       [7:0]   din     ,   //输入

    output  reg         vout    ,   //输出有效信号
    output  reg [7:0]   dout        //输出
);

//信号定义
    reg                 vin_ff0 ;
    reg                 vin_ff1 ;
    reg                 vin_ff2 ;
    reg                 vin_ff3 ;
    reg                 vin_ff4 ;
    reg                 vin_ff5 ;

    reg     [7:0]       din_ff0 ;
    reg     [7:0]       din_ff1 ;
    reg     [7:0]       din_ff2 ;
    reg     [7:0]       din_ff3 ;
    reg     [7:0]       din_ff4 ;

    wire    [10:0]      sum0_w0 ;   //The first level of water
    wire    [10:0]      sum0_w1 ;

    reg     [10:0]      sum0_r0 ;
    reg     [10:0]      sum0_r1 ;
    reg     [10:0]      sum0_r2 ;

    wire    [10:0]      sum1_w0 ;   //Second stage water
    reg     [10:0]      sum1_r0 ;

    wire    [15:0]      prod_w0 ;   //第三级流水线
    reg     [15:0]      prod_r0 ;

    wire    [11:0]      ave_w0  ;   //Fourth stage output
    reg     [11:0]      ave_r0  ;

//打拍
    always @(posedge clk or negedge rst_n) begin
        if(!rst_n)begin
            din_ff0 <= 1'b0;
            din_ff1 <= 1'b0;
            din_ff2 <= 1'b0;
            din_ff3 <= 1'b0;
            din_ff4 <= 1'b0;
            vin_ff5 <= 1'b0;
        end
        else if(vin)begin
            din_ff0 <= din    ;
            din_ff1 <= din_ff0;
            din_ff2 <= din_ff1;
            din_ff3 <= din_ff2;
            din_ff4 <= din_ff3;
            vin_ff5 <= vin_ff4;
        end
        else begin
            din_ff0 <= 0      ;
            din_ff1 <= din_ff0;
            din_ff2 <= din_ff1;
            din_ff3 <= din_ff2;
            din_ff4 <= din_ff3;
            vin_ff5 <= vin_ff4;
        end
    end

    always @(posedge clk or negedge rst_n) begin
        if(!rst_n)begin
            vin_ff0 <= 1'b0;
            vin_ff1 <= 1'b0;
            vin_ff2 <= 1'b0;
            vin_ff3 <= 1'b0;
            vin_ff4 <= 1'b0;
        end
        else begin
            vin_ff0 <= vin    ;
            vin_ff1 <= vin_ff0;
            vin_ff2 <= vin_ff1;
            vin_ff3 <= vin_ff2;
            vin_ff4 <= vin_ff3;
        end
    end

    assign sum0_w0 = din_ff0 + din_ff1; //The first level of water
    assign sum0_w1 = din_ff2 + din_ff3;

    always @(posedge clk or negedge rst_n) begin
        if(!rst_n)begin
            sum0_r0 <= 1'b0;
            sum0_r1 <= 1'b0;
            sum0_r2 <= 1'b0;
        end
        else if(vin_ff2)begin
            sum0_r0 <= sum0_w0;
            sum0_r1 <= sum0_w1;
            sum0_r2 <= din_ff4;
        end
    end

    assign sum1_w0 = sum0_r0 + sum0_r1 + sum0_r2;   //Second stage water

    always @(posedge clk or negedge rst_n) begin
        if(!rst_n)begin
            sum1_r0 <= 1'b0;
        end
        else if(vin_ff3)begin
            sum1_r0 <= sum1_w0;
        end
    end

    assign prod_w0 = sum1_r0*51;    //The third level computes the product

    always @(posedge clk or negedge rst_n) begin
        if(!rst_n)begin
            prod_r0 <= 1'b0;
        end
        else if(vin_ff4) begin
            prod_r0 <= prod_w0;
        end
    end

    assign ave_w0 = prod_r0>>8;     //The fourth level calculates the mean,并输出结果

    always @(posedge clk or negedge rst_n) begin
        if(!rst_n)begin
            dout <= 1'b0;
        end
        else if(vin_ff5)begin
            dout <= ave_w0;
        end
    end

    always @(posedge clk or negedge rst_n) begin
        if(!rst_n)begin
            vout <= 1'b0;
        end
        else begin
            vout <= vin_ff5;
        end
    end
 
endmodule