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STM32 learning record 0002-stm32
2022-04-22 07:06:00 【Li Xingye】
One 、 Why choose STM32
1.1 What is? STM32
It's a new foundation ARM Kernel 32 position MCU series
1、 The kernel is ARM The company requires high performance 、 Low cost 、 Low power embedded, specially designed Cortex-M kernel , It's a standard ARM kernel
2、 Advanced architecture
High performance 、 Low voltage 、 low power consumption 、 Innovative core and peripherals
1.2 Cortex kernel
STM32F1 Belong to Cortex-M In the series Cortex-M3 kernel , use ARMv7-M framework .
STM32F4 Belong to Cortex-M In the series Cortex-M4 kernel , use ARMv7-ME framework .
Cortex-A5/A8 use ARMv7-A framework .
Conventional ARM7 The series USES the ARMv4T framework
ARMv7 The architecture defines three distinct series :
“A” series : Facing the cutting-edge virtual memory based operating system and users
“R” series : For real-time systems
“M” series : For microcontrollers
1.3 Cortex-M3 VS ARM7
STM32 The kernel is Cortex-M3, Its structure is ARMv7-M,
LPC2130 The kernel is ARM7, The architecture is ARMv4T.
Here's an example of , The advanced life of former scholars : scholar -> Everyone -> Jinshi . And the reality is : Undergraduate -> The master -> Doctor . It's also the same as before. It's a title for readers , However, there has been progress and certain reform in the actual training process and methods .







Excellence and cost-effectiveness are compared
1、 High performance Cortex-M kernel
Cortex- The kernel uses ARMv7-M framework ( Harvard architecture ) Realization 1.25DMIPS/MHZ, Power consumption is only 0.19mv/MHZ, Than ARM&TDMI improvement 30%;
Single cycle multiplication and hardware division can be realized ;
Non separable is bit operation , Realize to ARM,I/O And optimal access to registers .
2、 Optimal code density
Thumb-2 Instruction set in 16 Bit instruction density implementation 32 Bit instruction set performance , And ARM&TDMI Of ARM The mode ratio is reduced 30%-45% The amount of code .
3、 Predictable running time
The interrupt controller is embedded in the kernel , The interval between interrupts can be at least 6 individual CPU cycle . Wake up in low-power mode requires only 6 individual CPU cycle .
4、 Improved regulation function
Serial single step adjustment and JTAG Adjust the .
summary :STM32 Higher cost performance , Lower price , Better performance ,
Two 、STM32 summary
2.1 CM3 Chip structure

2.2 STM32F10x Introduction to two product lines



2.3 STM32F10x Correlation between chips
2.4 STM32 Naming rules
See the picture , Familiar memory .

3、 ... and 、 summary
3.1 STM32 Application scenarios

3.2 STM32 Advantages summary

He likes to let him , You know what you know , Never know what you don't want to know , A little bit of learning , practice , That's the hard truth !
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本文为[Li Xingye]所创,转载请带上原文链接,感谢
https://yzsam.com/2022/04/202204220605386266.html
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