Cycle interrupt timer

About EPIT The contents of the timer are located in 《IMX6UL Reference manual 》 Of 1013 page .

Enhanced Periodic Interrupt Timer (EPIT)： Enhanced cycle interrupt timer , The counting mode of this timer is to count down . That is, count once and subtract one . And the main work of this timer is to complete periodic interrupt timing .

EPIT The composition of

EPIT It consists of five parts ： Clock source ,12 Bit frequency divider , Three 32 Bit register , interrupt , Output pin .

Clock source It can come from ：ipg_clk、ipg_clk_32、ipg_clk_highfreq.

12 Bit prescaler The division coefficient of is ：1~4096. The following is by 4 Frequency division to 2 Clock variation diagram of frequency division .

3 individual 32 Bit register ： Count register (EPIT_CNR)、 Load register (EPIT_LR) And comparison register (EPIT_CMPR), The count register holds the current count value , The comparison register also stores a value , When this value is equal to the count register, a comparison event is generated . The load register is used when the count register counts 0 when , Reload count .

interrupt ： The count register and the comparison register pass through CMP The comparator , When the two values are equal , There will be a comparison interrupt , That is, timed interrupt .

Output pin ：EPIT Pin output can be configured , Through the corresponding pin （EPITn_OUT） The output signal . The corresponding output pins are shown in the figure below

EPIT The block diagram is as follows ：

Count value 、 It's worth 、 The output signal 、 The relationship between interruption, etc

As shown in the figure ：

• The value set by the counter is 4、 The comparison value is 2

One clock pulse counts once , And count down , When you count to 2 when , There will be an interruption , also Output Signal Level reversal occurs , When you count to 0 when , Reload the count value to start a new round of counting .

Timer related registers MAP

From this table, we can find ,IMX6U There are two EPIT, And each EPIT Corresponding to a set of register groups , Each set of registers contains ：

• Control register （EPITn_CR）： For configuring timer
• Status register （EPITn_SR）： For reading timer status
• Load register （EPITn_LR）
• Compare register （EPITn_CMPR）
• Count register （EPITn_CNR）： Only this permission is read-only

CR Register details

EPITn_CR->CLKSRC： Used to select clock source ;

EPITn_CR->OM： Used to configure the output mode of the output pin ;

EPITn_CR->STOPEN： Enable stop mode （ Reset by the hardware itself ）;

EPITn_CR->WAITEN： Enable wait mode （ Reset by the hardware itself ）;

EPITn_CR->DBGEN： Can make debug Pattern （ Reset by the hardware itself ）;

EPITn_CR->IOVW： To configure EPIT Counter override write , When enabled, all writes to the load register will overwrite the contents of the counter ;

EPITn_CR->SWR： Software reset （ Set up 1 Reset , And self clearing ）;

EPITn_CR->PRESCALAR： Configure the prescaled value of counter clock ,0~4095;

EPITn_CR->RLD： Counter reload mode , by 0 yes free-running Pattern , by 1 yes set-and-forget Pattern ;

EPITn_CR->OCIEN： Enable output of compare interrupt events ;

EPITn_CR->ENMOD： Timer enabled mode ;

EPITn_CR->EN： Enable timer . by 0 Close when EPIT, by 1 Time to enable EPIT.

SR register

OCIF： Output comparison interrupt flag . When the counter value is equal to the value of this register, an interrupt will be generated . Write 1 Clears the interrupt flag bit .

Timer configuration steps

1. Set the clock source 、 Division coefficient 、 Counter reload mode 、 The initial value of the counter comes from
2. Enable comparison interrupt , Set load value and compare value （ That is, configure timer interrupt cycle ）
3. Can make EPITn interrupt , Register interrupt service function
4. Add an initialization function to the main function and enable the timer

Sample code

.c file

#include "bsp_epittimer.h"
#include "bsp_int.h"
#include "bsp_led.h"

/* * @description :  initialization EPIT Timer .EPIT The timer is 32 Bit down counter , The clock source uses ipg=66Mhz * @param - frac :  Frequency division value , The scope is 0~4095, They correspond to each other 1~4096 frequency division . * @param - value :  Countdown value . * @return :  nothing  */

void epit1_init(unsigned int frac, unsigned int value)
{
    
    /* Limit the prescaler factor to no more than 4095*/
    if(frac > 0XFFF)
        frac = 0XFFF;
    EPIT1->CR = 0;			//  Clear it first CR register 
    EPIT1->CR = 1<<24;		//  Configure clock source Peripheral clock=66MHz
    EPIT1->CR = frac << 4;	//  Configure prescaler coefficient 
    EPIT1->CR = 1 << 3;		//  Configure counting mode ： Count to 0 Then reload the count value 
    EPIT1->CR = 1 << 2;		//  Enable comparison interrupt 
    EPIT1->CR = 1 << 1;		//  The initial value of configuration count comes from LR register 
    EPIT1->LR = value;		//  Countdown value 
    EPIT1->CMPR	= 0;		//  Compare register , When the counter value is equal to the value of this register, an interrupt will be generated 
    /*  Can make GIC Corresponding interrupt in  */
    GIC_EnableIRQ(EPIT1_IRQn);
    /*  Register interrupt service function  */
    system_register_irqhandler(EPIT1_IRQn, (system_irq_handler_t)epit1_irqhandler, NULL);	
    EPIT1->CR |= 1<<0;	/*  Can make EPIT1 */ 
}

/* * @description : EPIT Interrupt handling function  * @param :  nothing  * @return :  nothing  */
void epit1_irqhandler(void)
{
     
    static unsigned char state = 0;
    state = !state;
    if(EPIT1->SR & (1<<0)) 			/*  Judge and compare the occurrence of events  */
    {
    
        led_switch(LED0, state); 	/*  Timer cycle to , reverse LED */
    }
    EPIT1->SR |= 1<<0; 				/*  Clears the interrupt flag bit  */
}

.h file

#ifndef _BSP_EPITTIMER_H
#define _BSP_EPITTIMER_H

#include "imx6ul.h"

void epit1_init(unsigned int frac, unsigned int value);
void epit1_irqhandler(void);

#endif