1. Interface

LPDDR The interface of

2. Command truth table

3. Write timing (Burst Mask Write)

The following waveforms are in 16Gb For example .

Writing data is mainly divided into 3 Operations . Activate (ACT-1 & ACT-2) -->MASK WRITE-1(MWR-1)–> Data writing
To write dram On 0x00000024 Take this address as an example . According to the following table (16103 count ) obtain , At this address rank(channel) The address is 0, bank The address is 0, column The address is 0x12,row The address is 0.

The first is the timing of activation , According to the truth table

• first clock： CA0=H, CA1=L yes ACT-1 command .R12-R15=0
• the second clock：BA0-BA2=0,R16,R11,R10=0
• Third clock ：CA0=H, CA1=H yes ACT-2 command ,R6-R9=0
• The fourth one clock：R0-R5=0
  So by activating , You can get bank The address is 0,ROW The address is 0.
  
  And then there was MASK-WRITE-1
• first clock: CA0-CA5=LLHHLL, by Mask Write-1(MWR-1),
• the second clock: BA0-BA2=0, C9=0, AP=1
• Third clock: CA0-CA4=LHLLH, by CAS-2 command .C8=-0
• The fourth one clock:C2-C7=4
  According to the previous calculation COL The address is 0x12, however C0-C1 yes 0, therefore 0x12 With 16 Aligned COL The address is 0x10(16), That is to say C2=0, C3=0, C4=1. It corresponds to , As for which one to choose word, Yes, it is DMI Signal to select .
  
  The last part is the part of data transmission . You can see in the DQ Upload the second of the data clock The rising edge is the data we write , In this clock Next DMI0_A The signal is L, Indicates that the written data is valid . stay DMI_A The signal is H Of clock The data on will not be written to DDR On .
  

4. Reading sequence (Read - 1)

Writing data is mainly divided into 3 Operations . Activate (ACT-1 & ACT-2) --> READ-1(RD-1)–> Data readout . Data read only Burst Read. Hypothetical reading 0x00000024 The address of ,LPDDR What you send out is actually 0x00000020 Is the starting address 32B data .

The first is the timing of activation , According to the truth table

• first clock： CA0=H, CA1=L yes ACT-1 command .R12-R15=0
• the second clock：BA0-BA2=0,R16,R11,R10=0
• Third clock ：CA0=H, CA1=H yes ACT-2 command ,R6-R9=0
• The fourth one clock：R0-R5=0
  So by activating , You can get bank The address is 0,ROW The address is 0.
  
  And then there was Read-1
• first clock：CA0-CA4=LHLLL(RD-1).BL=0
• the second clock：BA0-BA2=0, C9=0, AP=1
• Third clock：CA0-CA4=LHLLH(CAS-2),C8=0
• The fourth one clock：C2-C7=4
  
  Finally, data transmission . A total of 32B The data of , You can see the second ddr clock The place of , Is the data just written 0x9.