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SystemVerilog verification - Test Platform preparation guide learning notes (5): function coverage
2022-04-22 23:51:00 【lu-ming. xyz】
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A measure of which features of the program have been tested .
1 Why do you need functional coverage ?
If it's a directional test , Coverage in testing is implicit , The design specification lists 100 Features , What needs to be done is to complete 100 One test , If it's done 50 individual , Then the coverage is 50%.
For complex designs , Need to use a constrained random test method (CRT), At this time, you do not need to enter the incentive line by line manually , But you need to write code according to the verification plan to track the effectiveness of the test . The displayed functional coverage measures the progress of the test .
2 How to collect coverage ?
By changing the random number seed , You can run the same random test platform repeatedly to generate new incentives . Each simulation will produce a database with coverage information , Record the trajectory of random walk . By combining all this information together, we can get the function coverage , To measure the overall progress .
3 How to converge coverage ?

- Change the random number seed to obtain the function coverage data .
- Analyze the coverage data and decide how to modify the test set .
- The coverage rate has increased steadily : Add a new random seed and continue running the existing test , Or longer running time .
- The growth rate of coverage slowed down : Adding additional constraints creates more incentives .
- Coverage is stable and some parts have not been tested : Create more new tests .
- Close coverage 100% And keep finding mistakes : Not really covering some areas of the design .
4 What types of coverage ?
- Code coverage
- Functional coverage
- Vulnerability rate
- Assertion coverage
4.1 Code coverage
4.1.1 Code coverage measures ?
Code coverage is a measure of how well a test can be applied to a code that involves a specification “ Realization ” How thorough the test is , Not for the validation plan . The code coverage reaches 100% It doesn't mean that the work has been completed .
4.1.2 What code coverage measures ?
Code coverage is the easiest way to measure validation progress . Measure... In this way :
- How many lines of code have been executed ( Line coverage ).
- In the path through the code and expression, what has been executed ( Path coverage ).
- Which orders bit Variable value is 0 or 1( Flip coverage ).
- Which states and state transitions in the state machine have been accessed ( Finite state machine coverage ).
4.1.3 How to test code coverage ?
The tool automatically analyzes the source code and adds hidden code to complete the statistics of code coverage .
When all tests are run , The code coverage tool will create the corresponding database .
4.2 Functional coverage
Functional coverage is closely related to the design intent , Sometimes called “ Specification coverage ”, Code coverage is the implementation of bright design .
If a block of code is missing from the design , Code coverage can't find this error , But the functional coverage can .
4.2.2 How to measure functional coverage ?
- First, write the verification plan and the corresponding executable version for simulation .
- stay SystemVerilog The values of variables and expressions are sampled in the test platform . Where these samples are taken is the coverage point .
- At the same time ( For example, when a transaction is completed ) Multiple coverage points of are put together in a coverage group .
4.2.3 What is an overlay group ?
Coverage groups are similar to classes : It can be instantiated many times after one definition .
Contains coverage points 、 Options 、 Formal parameters and optional triggers (trigger). An overlay group contains one or more overlay points , Collect at the same time .
4.3 Vulnerability rate
An indirect way to measure coverage is to look at the rate of new vulnerabilities .

4.4 Assertion coverage
Assertions are used for one-time or For a while check Declarative code for the relationship between two design signals .
As opposed to using SystemVerilog Procedural code check , Assertion (SVA) Easier to express .
5 Strategy of function coverage ?
- Collect information instead of data .
FIFO Examples of verification , There is no need to measure the data in the read-write address index , There are many possibilities . If you can make FIFO From empty to full, then from full to empty , It has covered all situations in data reading and writing , Plus other interested States, such as full address index 1 And all 0 But between . - Only measure what will be used
- Completeness of measurement

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