The problem of synchronization and asynchrony of clocks is a very basic but very common problem. This article briefly summarizes the relevant problems that the author understands, and is used to make a simple judgment on the synchronization and asynchrony between clocks.

Clock-related properties include frequency, phase, and homology.It is a decisive factor to judge the synchronization and asynchrony of the clock and whether it is homologous or not.Clocks from different sources must be asynchronous, but those from the same source are not necessarily synchronous.First of all, the reason why the synchronous and asynchronous clocks need to be divided is that the setup time and hold time of the flip-flops need to be met. Even if the asynchronous clocks have the same frequency, there is no way to determine the phase, and there is no way to perform static timing analysis.Therefore, a distinction needs to be made between the two clocks.

Sync Clock

The important basis for the first judgment is whether it is a homologous clock. It is not a homologous direct asynchronous processing, and it is a homologous clock. Then look at its phase and frequency.
1. For the integer frequency division of the same clock, it can be processed as synchronization.
2. Synchronization processing can be done for the integer multiple frequency division of the same PLL.

Asynchronous Clock

1, different sources must be asynchronous
2, the frequency division multiple of the same PLL is a decimal, we generally do asynchronous processing

Here, there is no strong requirement for the phase of the homologous clock, mainly because the phase is actually a less important issue.The initial phase difference is different, but the frequency is the same, which can be repaired through the back end, mainly to ensure the constant frequency, otherwise the phase will become uncertain.The generation of the general phase is mainly due to the phase difference generated within the PLL itself, or due to the path delay.But it can be corrected to make it within an acceptable range.

Questions from the post on EETOP:
1. Two different crystal oscillators both generate 100M clocks, and the phase difference between the two is fixed. Are these two clocks synchronous or asynchronous?
In fact, this problem itself is problematic, different crystal oscillators, the phase difference cannot be fixed.So it must be asynchronous.
2. A PLL with a reference clock of 100M divides the frequency to produce a clk1=50M, and then multiplies a PLL to produce a clk2=500M. Are clk1 and clk2 synchronous clocks? The reference clock and the multiplied or divided clock areSynchronous or Asynchronous?
Synchronized, a clock from a PLL, as long as it is an integer multiple, is synchronized
Address: Synchronous Clock and Asynchronous Clock

Refer to two blog posts of IC_learner:
Cross-clock domain signal transmission (1) - control signal
Clocks and Constraints in Digital Design