一、实验概述

1、概念理解

SDRAM（Synchronous Dynamic Random Access Memory）,同步动态随机存储器.是FPGA中常用的一种高速、Large capacity off-chip存储器.

同步、动态、随机是其性能特点的外在说明：
同步（Synchronous ）是指内存工作需要同步时钟,内部的命令的发送与数据的传输都以它为基准
动态（Dynamic ）是指存储阵列需要不断的刷新来保证数据不丢失
随机（Random ）是指数据不是线性依次存储,而是自由指定地址进行数据读写

2、实验目的

3、实验要求

4、存储器

（1）定义

basic structure of computer system：

（2）工作原理

Schematic diagram of the basic structure of the memory：

（3）容量计算

（4）容量扩展

a.位扩展

b.字扩展

Double the depth,由式子M*2^N可知,Add one bit to the address bus width

c.Simultaneous expansion of bits and words

5、The storage characteristics of

SDRAM结构框图

基本参数

6、BANK、Row、Column

地址总线 行地址、Column address multiplexing on the same bus
数据总线 数据输入、Data output multiplexing the same bus
命令、数据、Control signals are latched on the rising edge of the clock

BANK示意图

7、引脚介绍

二、操作指令

常用的 SDRAM The operation instructions are as follows：

1、禁止命令(Command Inhibit)

禁止命令 (Command Inhibit) ,Other data sheets also refer to the Deselect Device Command (Device Deselect).不论 SDRAM 处于何种状态,This command can be executed;执行此命令后,SDRAM Chip is not selected,New commands cannot be written,But already executed commands are not affected.

2、无操作命令(No-operation)

无操作命令(No-operation),Also known as empty command、NOP命令.不论 SDRAM 处于何种状态,此命令均可被写 入,This command gives the selected SDRAM The chip passes a no-op message,目的是为了防止 SDRAM 处于空闲或等待状态时,其他命令被写入.

3、Register the command configuration mode(Load Mode Register)

Register the command configuration mode(Load Mode Register),也被称为 Mode Reigister Set.This command only has all Bank can only be written when both are in the idle state,Otherwise the configuration error,And after executing this command,SDRAM 必须等待相应的响应时间 tRSC(Register Set Cycle),Cycle mode register configuration)后,Can only be written to the new order.

In writing this command SDRAM When performing mode register configuration,需要地址总线 A0-A11 Mode setting of auxiliary registers,A0-A11 Assign different corresponding registers to configure different modes,Unused address bus is set low. A0-A11 The different assignments of the corresponding registers have different modes,具体见下图：

（1）突发长度(Burst Length)

突发(Burst)是指在同一行中相邻的存储单元连续进行数据传输的方式,连续传输所涉及到存储单元（列）的数量就是突发长度（Burst Length,简称 BL）.The lower three bits of the address bus A0-A2 is the burst length control bit,SDRAM The burst length of the chip can be set to 1、2、4、8 And the whole page,单位为字节,A full page represents the amount of data to transfer an entire row in one burst.

（2）突发类型

The set bits for the burst type are A3,Burst type can be set to two types,顺序和隔行.一般将 A3 设置为低电平,Select order type.

（3）Column Gating Delay(CAS Latency)

Column Strobe Latency is the clock cycle between when a read command is registered on the data bus and the first valid data appears interval,The column strobe latency can be set to 2 个或 3 个时钟周期,set bit to A6,A5,A4.

（4）运行模式(Operating Mode)

The run mode setting bits are A7,A8,SDRAM 存在标准模式、测试模式等多种模式,但对于普通用户,Only open standard mode,在使用 SDRAM 时只需将 A7,A8 Set to low to enter standard mode.

（5）写模式

The write mode setting bit is A9,控制 SDRAM 的写模式.当 A9 为低电平时,SDRAM 的读/写操 burst,突发长度由突发长度寄存器(A0-A2)设定;当 A9 位高电平时, SDRAM The read operation is still in burst mode,突发长度由突发长度寄存器(A0-A2)设定,但 SDRAM of write operations are not using burst mode,每一个写命令只能写入一个数据.

（6）A10-A12

A10-A12为保留位,对模式寄存器的配置不起作用,赋值为 0 即可.

4、预充电命令(Precharge)

The function of precharge is to close the specifiedBank 或者全部Bank active row in,Precharge command execution 后,must wait for the corresponding waiting time tRP(tRP(Precharge command Period),预充电命令周期),相对应的 Bank will be able to be re-operated.

预充电命令(Precharge)Command consists of two categories：All the charge in advance(Precharge All)和指定Bank 预充电 (Precharge Bank),当 A10 When sending a precharge command high,Follow all charge in advance orders,对所有的 Bank 进行预充电;当 A10 When sending a precharge command high,only by BA[1:0]选定的 Bank 进行预充电.

5、刷新命令(Refresh)

SDRAM 只有通过刷新操作才能保证数据的可靠性,SDRAM 的刷新操作是周期性的,在两次刷新的间隔可以进行数据的相关操作.我们在看SDRAM芯片参数时,经常会看到4096 Refresh Cycles/64ms或8192 Refresh Cycles/64ms的标识,这里的4096与8192就代表 Each of this chipBank的行数.

刷新命令一次仅对一行有效,也就是说在64mswithin these two specifications The chips need to be completed separately4096次和8192次刷新操作.这4096Operations can be averaged15.625μs刷新一次,也可以一次全部刷新完,却决于你的数据读写时序.

6、数据掩码

If the burst lengthBL=4,那么也就是说一次就传送4笔数据. 但是,如果其中的第二笔数据是不需要的,怎么办？Do you still want to transmit?？为了屏蔽不需要的数据,人们采用了数据掩码（Data I/O Mask,简称DQM）技术.通过DQM,内存可以控制I/OWhere to cancel the port some output or input data.In order to precisely mask each byte in a data bus width,每个DQM信号线对应一个字节（8bit）.

7、waiting time parameter

The following time parameters may vary depending on the chip：
tRP：PRECHARGE command period,发送预充电指令后进行下一个操作需要等待的时间
tRFC：AUTO REFRESH period,发送自动刷新指令后进行下一个操作需要等待的时间
tMRD：LOAD MODE REGISTER command to ACTIVE or REFRESH command,发送设置模式寄存器指令后进行下一个操作需要等待的时间

The refresh priority is higher than the read and write priority,But when are reading and writing,不刷新,Refresh after reading and writing is complete

三、项目设计

1、状态机设计

WAIT:上电等待,200us
PRECH:预充电
AREF:自动刷新
MRS:模式寄存器设置
ACTI:行激活
READ、WRITE:列读、写

2、项目需求

3、设计方案

The clock has a certain skew because,If sampling with the clock of the controller,unstable commands may be taken（Command changes with rising edge of controller clock,If they do not shift,The data collected at this rising edge is unstable）

The block diagram of the module is shown below：
sdram_ctrl与sdram_interface通过avalon_mm接口连接

4、信号列表

顶层模块

sdram_ctntroller模块

四、项目源码

1、sdram_interface

ipThe core configuration steps are as follows：

Configure memory parameters.
数据位宽,bank地址,行列地址

时间参数配置：


配置完成后点击保存

例化模板：