1. summary

Basic concepts

• Definition of bus ： Bus is a group of common information transmission lines that can be shared by multiple components in time-sharing . Time sharing and sharing are two characteristics of bus .
  Time sharing means that only one component is allowed to send information to the bus at the same time , If there are multiple components in the system , Then they can only send messages to the bus in time sharing .
  Sharing means that multiple components can be attached to the bus , The information exchanged between various components can be shared time-sharing through this group of lines . Only one component is allowed to send messages to the bus at a certain time , However, multiple components can receive the same message from the bus at the same time .

• Bus devices ： Devices connected to the bus , According to whether it has control function on the bus, it can be divided into master and slave Two kinds of .

• Bus characteristics ： mechanical properties （ Size 、 shape ）, Electrical characteristics （ Transmission direction and effective level range ）, features （ The function of each transmission line ）, Time characteristics （ Relationship between signal and timing ）.

• Burst transmission mode of bus ： A bus transmission mode that transmits multiple data words with continuous storage addresses in one bus cycle .

classification

• On chip bus ： The on-chip bus is the bus inside the chip , It is CPU Between registers inside the chip 、 Register and ALU A common connection between .

• The system bus ： System bus is the functional component of computer system （CPU、 Main memory 、I/O Interface ） A bus connected to each other .
  Different contents of information transmitted according to the system bus , It can be divided into three categories ： data bus 、 Address bus and control bus .

1. The data bus is used to transmit data information between functional components , It is a bidirectional transmission bus , The number of digits is the same as the machine word length 、 Store word length .
2. The address bus is used to indicate the main memory unit or location of the source data or destination data on the data bus I/O The address of the port , It is a unidirectional transmission bus , The number of bits of the address bus is related to the size of the main memory address space .
3. The control bus transmits control information , Include CPU Control commands and main memory sent out （ Or peripherals ） return CPU The feedback signal of .
   Pay attention to distinguish between data path and data bus ： The data transmission path formed by the connection of various functional components through the data bus is called the data path . A data path represents the path through which data flows , The data bus is the medium of carrying .

• Communication bus ： Between computer systems or between computer systems and other systems （ Such as telecommunication equipment 、 Test equipment ） A bus that transmits information between , Also known as external bus .

Besides , The bus can be divided into synchronous bus and asynchronous bus by means of time sequence control , The bus can also be divided into parallel bus and serial bus according to the data transmission format .

Structure of system bus

• Single bus structure ： The single bus structure will CPU、 Main memory 、I/O equipment （ adopt I/O Interface ） All hung on a set of buses , allow I/O Between devices 、I/O Exchange information directly between the device and main memory , As shown in the figure below .CPU And main memory 、CPU Information can be exchanged directly with peripherals , Without the intervention of intermediate equipment .

Note that a single bus does not mean there is only one signal line , The system bus can be subdivided into address bus according to different information transmitted 、 Data bus and control bus .
The advantage of single bus structure lies in its simple structure , The cost is low , Easy access to new devices ; The disadvantage is low bandwidth 、 Heavy load , Multiple components can only compete for a unique bus , And does not support concurrent transfer operations .

• Dual bus structure ：
  The dual bus structure has two buses ： One is the main memory bus , Used in CPU、 Transfer data between main memory and channel ; The other is I/O Bus , Used to transfer data between multiple external devices and channels , As shown in the figure below .

The advantage is that the low speed I/O The device is separated from the single bus , Storage bus and I/O Bus separation ; The disadvantage is that hardware devices such as channels need to be added .

• Three bus structure ： The three bus structure is adopted between the components of the computer system 3 Two independent buses form the information path , These three buses are the main memory bus 、I/O Bus and direct memory access （DMA） Bus , As shown in the figure below .

The main memory bus is used in CPU And memory 、 Data and control information .I/O The bus is used in CPU Communication between various peripherals .DMA The bus is used to transfer data directly between memory and high-speed peripherals .
Its advantage is that it improves I/O The performance of the equipment , Make it respond to commands faster , Improve system throughput . The disadvantage is that the working efficiency of the system is low .

Performance indicators

• Bus transmission cycle ： Refers to the time required for a bus operation （ Including the application stage 、 Addressing phase 、 Transmission phase and end phase ）, Bus cycle for short . The bus transmission cycle usually consists of several bus clock cycles .
• Bus clock cycle ： That is, the clock cycle of the machine . The computer has a unified clock , To control all parts of the whole computer , The bus is also controlled by this clock .
• The operating frequency of the bus ： Frequency of various operations on the bus , Is the reciprocal of the bus cycle .
• The clock frequency of the bus ： That is, the clock frequency of the machine , Is the reciprocal of the clock cycle .
• Bus width ： Also known as bus bit width , Is the number of data bits that can be transmitted simultaneously on the bus . Usually refers to the number of data buses .
• Bus bandwidth ： The data transfer rate of the bus , That is, the number of bits of data that can be transmitted on the bus in unit time , It is usually measured by the number of bytes of information transmitted per second . Bus bandwidth = Bus operating frequency x（ Bus bandwidth /8）
• Bus multiplexing ： A signal line that transmits different information at different times , Therefore, less lines can be used to transmit more information , So as to save space and cost .
• Number of signal lines ： Address bus 、 The sum of data bus and control bus is called the number of signal lines .

2. Bus arbitration

To solve multiple master At the same time, the problem of competing for bus control , Bus arbitration components shall be used , Choose one in some way master Give priority to bus control . Only devices that have gained control of the bus , To start transmitting data .

Centralized arbitration

The bus control logic is basically concentrated in one device （ Such as CPU in ）. Centralize all bus requests , Using a specific adjudication algorithm , Become a centralized way of adjudication , It has a chain query method 、 There are three ways of counter timing query and independent request .

• Chain query ： All components on the bus share a bus request line , When a part requests to use the bus , The bus request signal needs to be sent to the bus controller through this line . The bus controller checks whether the bus is busy , If the bus is not busy , Then send bus response signal immediately , It is transmitted serially from one component to the next via a bus response line , Query sequentially . If there is no bus request from the part where the response signal arrives , The signal is immediately transmitted to the next component ; If the arriving part has a bus request , The signal is intercepted , No more .
  In chain queries , The closer the component is to the bus controller, the higher the priority .
  The advantage is that the priority is fixed , In addition, the structure is simple , It's easy to expand ; The disadvantage is that it is sensitive to the fault of hardware circuit , And the priority cannot be changed . When high priority components frequently request the use of the bus , It will make the components with lower priority unable to use the bus for a long time .

• Counter timing query method ： A counter is used to control the use right of the bus , When the bus controller receives the bus request signal and judges that the bus is idle , The counter starts counting , The count value is sent to each component through the design address line . When the count value on the address line is consistent with the address of the requested bus device , The device obtains bus control , At the same time, stop the counting and query of the counter .
  The advantage is that the initial value of the counter can be set by the program , So priorities can change , And this method is not sensitive to the fault of the circuit ; The disadvantage is that the number of control lines is increased , Control is also relatively more complex .

• Independent request mode ： When the components on the bus need to use the bus , The bus request signal is sent through the respective bus request line , Queue in the bus controller , When the bus controller decides to approve the request of a component according to a certain priority , Send a bus response signal to the component , After receiving this signal, the component obtains the right to use the bus , Start sending data .
  Its advantage lies in its fast response speed ; The disadvantage is that there are many control lines , The bus control logic is more complex .

Distributed arbitration

Distributed arbitration does not require a central arbitrator , Each potential main module has its own arbitration number and arbiter . When they have a bus request , They will send their unique arbitration numbers to the shared arbitration bus , Each arbiter compares the arbitration number obtained from the arbitration bus with its own arbitration number . If the arbitration number on the arbitration bus has high priority , Then its bus request does not respond , And revoke its arbitration number , Last , The winner's arbitration number is retained on the arbitration bus .

3. Bus operation and timing

Bus timing refers to the control of the time cooperation relationship in the process of data exchange between the two sides , This control is called bus timing , Its essence is an agreement or rule , There are mainly two basic timing modes: synchronous and asynchronous .

Bus transmission 4 Stages

A bus cycle can usually be divided into the following four stages :

• Application allocation stage ： By those who need to use the bus master Apply , The bus arbitration organization decides to grant the bus use right of the next transmission cycle to an applicant . This stage can also be divided into two stages: transmission request and bus arbitration .

• Addressing phase ： Obtain the right to use master Send the message of this secondary access through the bus slave Address and related orders , Start the... Participating in this transmission slave.

• Transmission phase ：master and slave Data exchange , One way or two-way data transmission is possible .

• Closing phase ：master The relevant information of is removed from the system bus , Relinquish the right to use the bus .

Synchronous timing mode

It means that the system uses a unified clock signal to coordinate the transmission timing relationship between the sending and receiving sides . The clock produces equal time intervals , Each interval constitutes a bus cycle . In a bus cycle , The sender and receiver can make a data transmission . Because of the unified clock , Each component or device sends or receives information in a fixed bus transmission cycle . The advantage is that the transmission speed is fast , It has high transmission rate ; The bus control logic is simple ; The disadvantage is that the master-slave device belongs to mandatory synchronization , And the effectiveness test of data communication cannot be carried out in time , Poor reliability .
Synchronous communication is suitable for systems with short bus length and close access time of components connected to the bus .

Asynchronous timing mode

In asynchronous timing mode , There is no unified clock , There is no fixed time interval , The timing control is completely realized by transmitting the handshake signal restricted by both sides . The advantage is that the bus cycle length is variable , It can ensure reliable information exchange between two components or equipment with great difference in working speed , Automatic adaptation time coordination ; The disadvantage is that it is more complex than synchronous control , And it's slower .
according to request and respond Whether the cancellation of the signal is interlocked , Asynchronous timing methods can be divided into the following three types ：

• Non interlocking mode ：master issue request after , You don't have to wait until you get slave Of respond The signal , But after a period of time, it will be revoked request The signal . and slave After receiving request After the signal , issue respond The signal , And automatically revoke after a period of time respond The signal , There is no interlocking relationship between the two sides .

• Semi interlocking mode ：master issue request after , You must wait until you receive slave Of respond After the signal , Just revoke request The signal . and slave After receiving request After the signal , issue respond The signal , Don't wait to know master Of request The signal has been cancelled , But automatically revoke after a period of time respond The signal .

• Full interlock mode ：master issue request after , You must wait until you receive slave Of respond After the signal , Just revoke request The signal . and slave After receiving request After the signal , issue respond The signal , Must be informed master Of request The signal has been cancelled , To revoke respond The signal , There is an interlocking relationship between the two sides .

4. Bus standards

Bus standard is a standard published or recommended internationally for interconnecting various modules , It is a standard that must be followed when composing various modules into a computer system . The interface designed according to the bus standard can be regarded as a general interface , At both ends of the interface , Either party only needs to complete its own functional requirements according to the requirements of bus standards , Without knowing the requirements of the other party's interface .