FPGA engineer interview questions collection 121~130

121. At present, LUT-based FPGAs using SRAM technology still occupy an absolute mainstream position, but such FPGAs have inherent defects. What is the development trend of the next-generation FPGA architecture?Does Altera have any new attempts in this regard?

Answer: The next-generation FPGAs are mainly developed in the direction of SOPC:
Altera's next-generation product Stratix, the basic unit LE is still based on the LUT structure, but with some major changes,
① Removed the traditional cascadeChain (Cascade Chain);
② The carry chain (Carry Chain) has changed from the previous single one to LAB Carry-in, Carry-in1, Carry-in0 three;
③ The fan-out of LE is also changed from 2Changed to 4;
④ There are more control signals for flip-flops.
Other aspects:
① RAM: Change the previous single 2K BITs or 4K BITs Memory to small RAM: 512BITs; Medium RAM:4KBITs; Large RAM: 512 KBITs;
② Embed DSP in FPGA for the first time;
③ The clock link is also changed from global clock to global clock and regional global clock;
④ . . . . ..
All of these changes are deliberate improvements made through extensive user feedback to make Stratix devices more suitable for users' design needs

122."Always use fully synchronous design. You never need to reply on gate delay if your design is fully synchronous.After processing the control signal that comes in with the data, the output control signal will lag the data by several clock cycles. At this time, the data has to be gate-delayed to achieve synchronization. Now it seems that this is