1 SystemVerilog from C/C++ Introduced operators and statements ？

• Can be in for Loop defines the loop variable .
• Auto increment symbol "++“, Auto decrement symbol ”–".
• continue and break, Used to skip this cycle and End cycle .

2 SystemVerilog For functions 、 New content in task form ？

In summary SystemVerilog Grid is more like C 了 , Introduced stack , So there are similar C The parameter of .

1. SystemVerilog Function allows calling tasks , But only in fork…join_none Statement generated Threads Call in .
2. SystemVerilog have access to void Convert the results , To ignore the return value of the function . void '($fscanf(file, “%d”, i));
3. SystemVerilog Of a subroutine begin…end Become optional .task/endtask function/endfunction Enough as a boundary .
4. SystemVerilog increase return sentence .

3 SystemVerilog New content on subroutine parameters ？

1. On the parameter declaration ,Verilog Some parameters are required to be declared twice , A direction statement , A type declaration output [31:0] x; reg [31:0] x;.SystemVerilog Introduced a C Lattice of , But note that you must use a common input type logicoutput logic [31:0] x.
2. SystemVerilog The default parameter type and direction are "logic Input ".
3. SystemVerilog The transfer method of parameters can be specified as reference ref Instead of copying const ref bit [31:0] a[], Save stack space . Be careful ref Can only be used with automatic automatic Stored subroutines .
4. SystemVerilog You can specify a default value for the bit parameter input logic low = 0.
5. SystemVerilog Tasks or functions can be similar to port The syntax specifies .a(5).

4 SystemVerilog New precision and time units ？

• timeunit and timeprecision The declaration statement can indicate the time value for each module timeunit 1ns; timeprecision 1ps;.