Preface

Before last winter vacation, one of my relatives asked me how to make a five frequency divider . I don't think it's easy , Isn't it just a counter , But the discovery is not that simple , Because the even frequency divider can count according to the rising edge , But odd dividers can also , But I can't 50% Duty cycle . In today's class, the teacher solved this problem perfectly .

Even frequency division

We've studied counters before , Even allocation is nothing more than a counter , When using the signal as the intermediate variable, it should be noted that it is a lag variable , Therefore, when modifying, you should consider clearing . There's nothing to say about this. Go directly to the code .

library ieee;  
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Test is
	generic(constant N:integer:=6);
	port(signal clk:in std_logic;signal cout:out std_logic);
end Test;
architecture even of Test is
	signal temp:integer:=0;
	constant half:integer:=N/2;
begin
	process(clk)
	begin
	if rising_edge(clk) then
		temp<=temp+1;
		if temp<half then
			cout<='1';
		elsif temp<N-1 then
			cout<='0';
		else
			temp<=0;
			cout<='0';
		end if;
	end if;
	end process;
end even;

Here we can realize an even frequency division . This must be no problem for everyone , So let's continue to look at odd frequency division

Odd frequency division

It's easy to think of odd frequency division 50% The duty cycle of must be related to both rising and falling edges , So we count both rising and falling edges , Take a look at the effect .

We find that only when the states in both directions are 0 Only when 0
Because looking in the right direction , He will have a delay of half a clock cycle , So you can do it 3.5 A cycle of high level . Then the rest is naturally low level .

library ieee;  
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity div_any is
	generic(constant N:integer:=5);
	port(signal clk:in std_logic;signal cout:out std_logic);
end div_any;
architecture even of div_any is
	signal tempA,tempB:integer:=0;
	signal coutA,coutB:std_logic;
	constant half:integer:=N/2;
begin
	process(clk)
	begin
	if rising_edge(clk,coutA,coutB) then
		tempA<=tempA+1;
		if tempA<half then
			coutA<='1';
		elsif tempA<N-1 then
			coutA<='0';
		else
			tempA<=0;
			coutA<='0';
		end if;
	elsif falling_edge(clk) then
		tempB<=tempB+1;
		if tempB<half then
			coutB<='1';
		elsif tempB<N-1 then
			coutB<='0';
		else
			tempB<=0;
			coutB<='0';
		end if;
	end if;
	cout<=coutA or coutB;
	end process;
end even;

Arbitrary frequency division

So how to achieve arbitrary frequency division ？
We can find out , If the current number is even , Then it's just the same as the rising edge . But let's make a special judgment here ,1 The situation of .
The following code changes the frequency division status by entering the frequency division value .

library ieee;  
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity div_any is
	port(signal clk:in std_logic;
	signal scaler:in integer range 0 to 63;
	signal clk_out,clk_f,clk_r:out std_logic);
end div_any;
architecture DIV of div_any is
	signal f_count:integer range 0 to 63:=0;
	signal r_count:integer range 0 to 63:=0;
	signal half:integer;
	signal even:integer;
	signal clk_f_temp,clk_r_temp:std_logic;
begin
	half<=scaler/2;
	even<= scaler rem 2;
	with even*scaler select
	clk_out<=clk_r_temp 						when 0,
				clk 								when 1,
				clk_f_temp or clk_r_temp 	when others;
	process(clk,scaler)
	begin
		if rising_edge(clk) then
			r_count<=r_count+1;
			if r_count<half then
				clk_r_temp<='1';
			elsif r_count<scaler-1 then
				clk_r_temp<='0';
			else
				clk_r_temp<='0';
				r_count<=0;
			end if;
		elsif falling_edge(clk) then
			f_count<=f_count+1;
			if f_count<half then
				clk_f_temp<='1';
			elsif f_count<scaler-1 then
				clk_f_temp<='0';
			else
				clk_f_temp<='0';
				f_count<=0;
			end if;
		end if;
	end process;
	clk_f<=clk_f_temp;
	clk_r<=clk_r_temp;
end DIV;

By-Round Moon