The state machine control shift register multisim simulation in the process of state variables and state transition conditions don't match

The question is as follows:

When we reach 0000001, the state variable should take the value s1s0=10

But in the actual simulation process, s1s0 still remains unchanged at 01 at 0000001, and the jump from 01 to 10 occurs when 0000001 ends to 1000000 resets.At this point, we have verified that the circuit function is feasible, but the actual state variables do not match the state transition conditions, so we need to analyze the circuit parameters

Summarizing this problem is that the transition is delayed. Combined with the function of the D flip-flop, it can be seen that the D flip-flop is triggered by the rising edge of the CP pulse, so we can speculate that the cause of the problem should be that the CP pulse has not yet arrived or is delayed.arrived

We can measure the D and CLK terminals with an oscilloscope, and get the following waveforms:

Blue is pulse waveform, red is D port input waveform

It can be seen from the figure that the CP pulse is significantly later than the D input signal. The rising edge of the CP pulse does not trigger the D flip-flop for nearly half of the time, and the state will remain for a certain period of time after the trigger, so the transition conditions and states appear.Variable mismatch problem.

The key to solving this problem is to achieve the rising edge reaching the trigger as quickly as possible. We can reduce the trigger interval by increasing the frequency of the pulse signal, which can reduce the time between the D port signal and the rising edge of CP.It can also complete multiple recordings in the same time to avoid the state variable staying for too long.