CAN filter

1、 Configure the filter so that the filter group works in initialization mode , Enter normal mode after configuration

CAN1->FMR|=1<<0;		// Filter bank 0 Working in initialization mode 
//CAN1->FMR|=1<<n; // Filter bank n Working in initialization mode 
/*... To configure */
CAN1->FMR&=0<<0;		// Filter bank 0 Enter normal mode 
//CAN1->FMR&=0<<n; // Filter bank n Enter normal mode 

2、 When configuring a filter, it is also necessary to turn off the activation of the filter

CAN1->FA1R&=~(1<<0);	// filter 0 Do not activate 
//CAN1->FA1R&=~(1<<n); // filter n Do not activate 

CAN1->FA1R|=1<<0;		// Activate the filter 0
//CAN1->FA1R|=1<<n; // Activate the filter n

3、 Set the filter bit width , Yes 32 Bit and 16 Two modes , This affects the later filtering and shielding ID length

CAN1->FS1R|=1<<0; 		// filter 0 The seat width is 32 position 
CAN1->FS1R&=~(1<<0); 		// filter 0 The seat width is 16 position 
CAN1->FS1R|=1<<n; 		// filter n The seat width is 32 position 
CAN1->FS1R&=~(1<<n); 		// filter n The seat width is 16 position 

STID standard ID
EXID Expand ID
IDE
RTR

32 Bit mode

CAN_FxR1[31:21]	CAN_FxR1[20:3]	CAN_FxR1[2]	CAN_FxR1[1]	CAN_FxR1[0]
CAN_FxR2[31:21]	CAN_FxR2[20:3]	CAN_FxR2[2]	CAN_FxR2[1]	CAN_FxR2[0]
STID[10:0]	EXID[17:0]	IDE	RTR	0

16 Bit mode

CAN_FxR1[15:5]	CAN_FxR1[4]	CAN_FxR1[3]	CAN_FxR1[2:0]
CAN_FxR1[31:21]	CAN_FxR1[20]	CAN_FxR1[19]	CAN_FxR1[18:16]
CAN_FxR2[15:5]	CAN_FxR2[4]	CAN_FxR2[3]	CAN_FxR2[2:0]
CAN_FxR2[31:21]	CAN_FxR2[20]	CAN_FxR2[19]	CAN_FxR2[18:16]
STID[10:0]	IDE	RTR	EXID[17:15]

4、 Set the filter operating mode , Identifier mask bit mode and identifier list mode

CAN1->FM1R&=~(1<<0);		// filter 0 Working in identifier mask bit mode 
CAN1->FM1R|=1<<0;		// filter 0 Working in identifier list mode 
CAN1->FM1R&=~(1<<n);		// filter n Working in identifier mask bit mode 
CAN1->FM1R|=1<<n;		// filter n Working in identifier list mode 

5、 Filter associated to FIFOn n=0,1

CAN1->FFA1R&=~(1<<0);		// filter 0 Related to FIFO0
CAN1->FFA1R|=1<<0;		// filter 0 Related to FIFO1
CAN1->FFA1R&=~(1<<n);		// filter n Related to FIFO0
CAN1->FFA1R|=1<<n;		// filter n Related to FIFO1

6、 Set filtering rules

	CAN1->sFilterRegister[0].FR1=0x21<<21;//32 position ID
	CAN1->sFilterRegister[0].FR2=(0x7F<<21);//32 position MASK

Identifier pattern
Each of the registers corresponds to the level of the corresponding bit of the desired identifier .
0: It is expected that the corresponding bit is dominant ;
1: The corresponding bit is expected to be recessive .
Mask bit mode
Each bit of the register indicating whether the corresponding identifier register bit must be consistent with the corresponding bit of the desired identifier .
0: No concern , This bit is not used for comparison ;
1: Must match , The incoming identifier bit must be consistent with the identifier register bit corresponding to the filter

The identifier pattern is FR2 by 1 The bit of identifies the bit to be verified ,FR1 Explain what the identified bit must be , That is, a filter, a rule , The logic here is similar to & operation

	CAN1->sFilterRegister[0].FR1=0x21<<21;//32 position ID
	CAN1->sFilterRegister[0].FR2=(0x7F<<21);//32 position MASK
// Means to check SDID Standard frame ID The lower seven of , The lower seven must be 0x21 To pass 

Mask bit mode Is to specify a specific one ID,ID All bits of must conform to the set value

CAN1->sFilterRegister[0].FR1=0x21<<21;//32 position ID
CAN1->sFilterRegister[0].FR2=0xFF<<21)//32 position MASK
// Only 0x00 and 0xFF It can be filtered 

Program routine

void CAN_Set_Filter(u8 Addr)
{
    
	Addr=Addr&0x7F;
	// Filter initialization 
	CAN1->FMR|=1<<0;		// The filter group works in initialization mode 
/* Filtering rules 1 CAN ID The lower seven digits of must be the same as Addr Agreement , Others don't care  */
	CAN1->FA1R&=~(1<<0);	// filter 0 Do not activate 
	CAN1->FS1R|=1<<0; 		// The filter bit width is 32 position .
	CAN1->FM1R|=0<<0;		// filter 0 Working in identifier mask bit mode 
	//CAN1->FM1R|=1<<0; // filter 0 Working in identifier list mode 
	CAN1->FFA1R|=0<<0;		// filter 0 Related to FIFO0
	CAN1->sFilterRegister[0].FR1=Addr<<21;//32 position ID
	CAN1->sFilterRegister[0].FR2=(0x7F<<21);//32 position MASK
	CAN1->FA1R|=1<<0;		// Activate the filter 0
/* Filtering rules 2 CAN ID Of the 7 Bit must be 1, That is, only 0x80 Can pass */	
	CAN1->FA1R&=~(1<<1);	// filter 1 Do not activate 
	CAN1->FS1R|=1<<1; 		// filter 1 The seat width is 32 position .
	//AN1->FM1R|=0<<1; // filter 1 Working in identifier mask bit mode 
	CAN1->FM1R|=1<<1;		// filter 1 Working in identifier list mode 
	CAN1->FFA1R|=0<<1;		// filter 1 Related to FIFO0
	CAN1->sFilterRegister[1].FR1=0x80<<21;//32 position ID
	CAN1->sFilterRegister[1].FR2=(0x80<<21);//32 position MASK
	CAN1->FA1R|=1<<1;		// Activate the filter 1
/* Filtering rules 3 CAN ID The lower eight digits of must be 0x00*/
	CAN1->FA1R&=~(1<<2);	// filter 2 Do not activate 
	CAN1->FS1R|=1<<2; 		// filter 2 The seat width is 32 position .
	CAN1->FM1R|=0<<2;		// filter 2 Working in identifier mask bit mode 
	//CAN1->FM1R|=1<<2; // filter 2 Working in identifier list mode 
	CAN1->FFA1R|=0<<2;		// filter 2 Related to FIFO0
	CAN1->sFilterRegister[2].FR1=0x00<<21;//32 position ID
	CAN1->sFilterRegister[2].FR2=(0xFF<<21);//32 position MASK
	CAN1->FA1R|=1<<2;		// Activate the filter 2
	
	CAN1->FMR&=0<<0;		// The filter bank enters normal mode 
}