The vivado project corresponding to the board is generated by TCL script

Source of problem

Try according to PYNQ v2.4 Source code refactoring Base Overlay, Think from tcl Scripts are generated directly Vivado engineering

Resources and development kits

1. Vivado 2018.3
2. On time atomic Star Development Board Zynq7010 (xc7z010clg400-1 chip )

Operation record

1. Download it in advance PYNQ v2.4 Source code （ Official search v2.4 Of Release）
2. View and modify Tcl Script base.tcl ( route <PYNQ repository>/boards/Pynq-Z1/base)
3. The first part of the script 105 That's ok , take -part The parameters are modified to the chip model of the board , I am here xc7z010clg400-1

if {
     $list_projs eq "" } {
    
   create_project ${overlay_name} ${overlay_name} -part xc7z010clg400-1
}

Save and exit

4. open Vivado 2018.3, Found at the bottom Tcl Console
   
5. Type the command... In the input box

cd <PYNQ repository>/boards/Pynq-Z1/base
source ./base.tcl

6. Wait for a while , complete , open Block Design Check it out.
   
   Follow up on Base Overlay Of Block Design Tailoring , modify xdc Constraint file , Generate bit flow , Development on the board