01 Major events in the industry

How many? GPU Working days ≈10 People work in a team for more than half a year

NVIDIA uses AI Efficient chip design

「 The same is to transplant a new technology library , If manpower is used , We need a 10 People work in a team for more than half a year , But with the help of AI, We only need a few days to run a few GPU Can do most of the work .」

In recent years , The chip design becomes AI An important area of landing , Google 、 Ying Wei Da 、 samsung 、 Many companies such as Siemens have planned or begun to try to use... In chip design AI. among , At the same time, in chip design and AI NVIDIA, which has been working in the field for many years, has unique advantages . Some time ago GTC At the conference , NVIDIA chief scientist 、 Master of computer architecture Bill Dally The progress they have made in this field and the AI Tools .

Here are Bill Dally stay GTC The original introduction at the conference .

Predicted voltage drop

As AI Experts , We naturally want to take advantage of AI To design better chips . We have several different ways ： One is to use the existing computer-aided design tools （ And into AI）, For example, we have one that can draw GPU Map of the location of medium power consumption , It can also predict how much the voltage network will drop —— Multiply the current by the resistance voltage drop , go by the name of IR Pressure drop . In traditional CAD It takes three hours to run the process on the tool .

This is an iterative process , So it's a little troublesome . We want to train a AI Model to process the same data . We have made a series of designs to do this , Then you can enter the power diagram , The final inference time is only three seconds . Of course , If you count the time of feature extraction , We want to spend 18 minute , You'll get results soon .

We don't use convolutional neural networks , Instead, a graph neural network is used , This is to estimate the switching frequency of different nodes in the circuit . Again , We can get very accurate power estimation faster than traditional tools , And in very little time .

Predict parasitic parameters （parasitics）

One of my favorite jobs is to use graph neural networks to predict parasitic parameters . This work used to take a lot of time , Because the previous circuit design was an iterative process , You have to draw a schematic diagram , Like the picture on the left . But you don't know how it works , Until the designer uses the schematic diagram for layout, Extract parasitic parameters , Then run the circuit simulation , Will find that the design may not meet the specifications , To know the performance of the circuit .

Next , The designer has to modify the schematic diagram , And pass it again layout To verify the effectiveness of the circuit . It's a very long time 、 Repeated and even inhumane labor-intensive work .

Now? , We can train graph neural network to predict parasitic parameters , There is no need for layout. therefore , Circuit designers can iterate very quickly , Without having to do it manually layout step . It turns out that ： The prediction of parasitic parameters by our neural network is very accurate .

Layout 、 Cabling challenges

Our neural network can also predict routing congestion （routing congestion）, This is for chips layout crucial . In the traditional process , We need to make a net list （net list）, Run the layout and routing process , This can be very time consuming , It usually takes a few days . But if you don't , We can't get the actual wiring congestion and find the defects of the original layout . We need to refactor it and lay it out in different ways macro To avoid the red area shown in the figure below （ There are too many wires passing through this area , It's like a traffic jam ）.

Now with the help of neural networks , No need to run layout and cabling , We can get these lists and use graph neural network to roughly predict the location of congestion , The accuracy is also very high . This method is not perfect yet , But it can show where there are problems , Then we can take action and iterate very quickly , Without complete layout and wiring .

Automated standard cell migration

All the above methods are in use AI Evaluate the design that humans have completed , But what's actually more exciting is to use AI To actually design the chip .

Let me give you two examples . The first is what we call NV cell The system of , It uses simulated annealing and reinforcement learning to design our standard cell library （ The standard cell library is a collection of the underlying electronic logic functions , for example AND、OR、INVERT、 trigger 、 Latches and buffers ）. So at every technical iteration , For instance from 7 Nano migration to 5 nanometer , We all have a unit library . We actually have thousands of such libraries , They have to be redesigned with new technology , There is a very complex set of design rules .

We use reinforcement learning to place transistors , But then there may be a pile of design rule errors , And that's what reinforcement learning is good at . Designing a chip is like an Atari game , But it's a game of fixing design rule errors in standard units . Check and fix these design rule errors through reinforcement learning , We can basically complete the design of standard units .

The figure below shows that the completion degree of the tool is 92% Cell library , No design rules or wrong electrical rules . Of these units 12% Smaller than human designed units . in general , In terms of unit complexity , The tool does as well as human designed units , Even better than human .

This has two major benefits for us . First, save a lot of labor . The same is to transplant a new technology library , If manpower is used , We need a 10 People work in a team for more than half a year , But with the help of AI, We only need a few days to run a few GPU Can complete most of the work that can be automated （92%）, Then someone will do the rest 8%. Many times we can get better designs , So this way not only saves manpower , The effect is also better than that of human hand .

Link to the original text ：

https://www.hpcwire.com/2022/04/18/nvidia-rd-chief-on-how-ai-is-improving-chip-design/

How to explain AI Decisions made ？ This paper combs the application scenarios and interpretability of the algorithm

This paper combines 《Explanation decisions made with AI》 guide , The application scenarios and interpretability analysis of the algorithm are combed and summarized .

In the UK  Information Commissioner’s Office （ICO） and The Alan-Turing Institute Jointly released 《Explanation decisions made with AI》 guide . The purpose of this guide is to provide practical advice to institutions and organizations , To help explain to the individuals affected by AI Procedures for providing or assisting 、 Services and decisions , At the same time, help institutions and organizations comply with the EU  GDPR And other policy requirements related to personal information protection . The guide is divided into three parts , The first 1 part ： Explainable AI Basic knowledge of ; The first 2 part ： Explainable AI Practice ; The first 3 part ： Explainable AI To organization / The meaning of organization . The guide concludes with the mainstream AI Algorithm / Applicable scenarios of the model , And for these algorithms / Interpretability analysis of the model , It can be used as an interpretable tool that can meet the requirements of the field in the practical task combined with the characteristics of the application scenario AI Algorithm / Model reference .

This paper combines 《Explanation decisions made with AI》 guide , The application scenarios and interpretability analysis of the algorithm are combed and summarized . Besides , We also read a recent paper on interpretable methods in the field of Medicine —《 Evaluate the prediction of adverse drug events based on attention and SHAP Clinical effectiveness of time interpretation 》, To understand the latest research progress on interpretability methods .

Insufficient ability to recognize formal language , Imperfect Transformer To overcome the theoretical defects of self attention

In the last year or two ,transformer Already in NLP、CV And other diverse tasks , And there is unity AI Trends in the field . that , Is the attention mechanism that has been launched for nearly five years really what everyone needs ？ In recent days, , Some papers have tested transformer Theoretical defects in two formal languages , And a method is designed to overcome this defect . The possible problem of length generalization is also studied , And put forward the corresponding solution .

Even though transformer The model is very effective in many tasks , But they are difficult to deal with some formal languages that look very simple .Hahn (2020) Propose a lemma 5）, To try to explain this phenomenon . This lemma is ： Changing an input symbol will only transformer The output of changes 𝑂(1/𝑛), among 𝑛 Is the length of the input string .

therefore , For receiving （ That is to determine whether a string belongs to a specific language ） It depends only on the language of a single input symbol ,transformer May accept or reject strings with high accuracy . But for big 𝑛, It must make decisions with low confidence , That is, the probability of accepting a string is slightly higher than ½, The probability of rejecting a string is slightly lower than ½. More precisely , With 𝑛 An increase in , The cross entropy is close to each string 1 The bit , This is the worst-case possible value .

In the near future , In the paper 《Overcoming a Theoretical Limitation of Self-Attention》 in , Two researchers at the University of Notre Dame used the following two regular languages （PARITY and FIRST） To test this limitation .

Hahn Lemma applies to PARITY, Because the network must pay attention to all the symbols of the string , And the change of any one of these symbols will change the correct answer . The researchers also chose FIRST As one of the simplest language examples to which lemmas apply . It only needs to pay attention to the first symbol , But because changing this symbol will change the correct answer , So the lemma still applies .

Although the lemma may be interpreted as what limits it transformer The ability to recognize these languages , But the researchers showed three ways to overcome this limitation .

02 Programmer area

Git 2.6 Release

Distributed version control tools Git 2.6 Official release , This version is made by 717 A non consolidated submission has been completed , This version fixes the backward compatibility flaw 、 Yes UI、Workflow& function 、 performance 、 Internal implementation 、 Development support has carried out repair and function development , among * "git name-rev --stdin " Has been abandoned , Warning will be issued when using .

W3C Release WebAssembly 2.0 First draft

The draft includes 3 Parts of , Namely ：WebAssembly Core Specification, It describes 2.0 Version of WebAssembly Core standards , It's kind of safe 、 portable 、 A low-level code format designed for efficient execution and compact representation ;WebAssembly JavaScript Interface --2.0 The version provides a clear JavaScript API, Used with WebAssembly Interact ;WebAssembly Web API --2.0 edition , It describes WebAssembly Integration with broader network platforms .

Boost 1.79.0 Release , portable C++ library

portable C++ library Boost Released 1.79.0 edition , This version has made a lot of updates to the library , involve Asio、Assert、Atomic、Beast、Core、Describe、Filesystem、Geometry、Integer、IO、Iterator、JSON、LEAF、Log etc. .