VHDL implementation of 32-bit binary to BCD code

Use FPGA The nixie tube on the development board displays the value , You need to convert the value to the corresponding BCD code , Then the value is displayed on the nixie tube through the seven segment decoder . I divide by ten , use VHDL Yes 32 Bit binary conversion BCD Code code .

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;

ENTITY BIN32_TO_BCD1 IS
	PORT(
		BIN: IN STD_LOGIC_VECTOR(31 DOWNTO 0);
		BCD: OUT STD_LOGIC_VECTOR(39 DOWNTO 0)
	);
END ENTITY BIN32_TO_BCD1;

ARCHITECTURE RTL OF BIN32_TO_BCD1 IS
BEGIN
	PROCESS(BIN)
		VARIABLE TEMP: INTEGER;
		VARIABLE BIN_TEMP: INTEGER;
		VARIABLE BCD_TEMP: STD_LOGIC_VECTOR(39 DOWNTO 0);
	BEGIN
	        BCD_TEMP:=X"0000000000";
	        BIN_TEMP:=CONV_INTEGER(BIN);
		FOR K IN 0 TO 9 LOOP
			TEMP:=BIN_TEMP REM 10;
			BCD_TEMP(3+4*K DOWNTO K*4):=CONV_STD_LOGIC_VECTOR(TEMP,4);
			BIN_TEMP:=(BIN_TEMP-TEMP)/10;
			IF BIN_TEMP=0 THEN
				EXIT;
			END IF;
		END LOOP;
		BCD<=BCD_TEMP;
	END PROCESS;
END RTL;

I wanted to add it by moving left 3 The algorithm of , But it didn't work . The above method of dividing by ten is to divide STD_LOGIC_VECTOR convert to INTEGER, Then divide by ten and take the remainder and propose decimal places one by one . Be limited to VHDL Of INTEGER Is a signed integer , The above code can only realize 31 Bit unsigned binary to BCD code .