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文献阅读(185)Co-design

2022-08-11 11:08:00 tiaozhanzhe1900

  • 题目:Coupling Extraction and Optimization for Heterogeneous 2.5D Chiplet-Package Co-Design
  • 时间:2020
  • 会议:ICCAD
  • 研究机构:阿肯色大学

缩写

  • RDL: package redistribution layers 再分布层
  • WLP: Wafer-Level-Packaging

传统的设计流程是将芯片设计与封装设计分开进行,没有考虑他们的相互作用,因为间隙足够大,PCB pitch(间距)为250um,但后面发展的wafer级封装技术间隙为30-50um,然后现在InFO就到了10-1.5um;因此,为了保证系统可靠性和信号完整性,需要在时序和功耗上考虑芯片和封装上的相互作用

本篇论文的主要贡献:

  1. A unified tool flow that, for the first time, designs and optimizes chiplets and the package of high-density 2.5D systems together taking into account the mutual interactions between them;
  2. A new holistic parasitic extraction and STA analysis flow for homogeneous 2.5D systems with chiplets and the package considered together;
  3. A new in-context parasitic extraction and STA analysis flow for heterogeneous 2.5D systems with chiplets-package interactions captured;
  4. A comparative study between two 2.5D designs to validate our Drop-in design approach and demonstrate chiplet-package interaction impacts on two 2.5D systems Performance, Power, and Area (PPA)

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Package Floorplanning and RDL Routing

chiplet间的RDL线完全有可能成为时序的瓶颈,当然,相比与芯片内部,RDL密度要小得多,所以不太可能出现不能布线即routability的问题,关键还是时序能不能满足要求,需要package wireload estimations
在这里插入图片描述

  • 题目:Thermal Modeling of a Chiplet-Based Packaging With a 2.5-D Through-Silicon Via Interposer
  • 时间:2022
  • 期刊:TCAD
  • 研究机构:TPMT( IEEE Transactions on Components, Packaging and Manufacturing Technology)

2.5D封装

The 2.5-D packaging uses an interposer with TSVs and redistribution layers (RDLs).
Multiple chips are stacked on the interposer side-by-side via microbumps (μ-bumps) to connect to each other or the substrate.

在这里插入图片描述
由上图所示
Two chiplets are mounted on the interposer side-by-side through μ-bumps. The interposer is bonded on an organic substrate via the controlled collapse chip connection (C4) bumps.
In general, the packaging interconnections can be classified into horizontal and vertical ones. The horizontal interconnection mainly includes fine line/space layers, 2.5-D interposer, and silicon bridge, while the vertical interconnection mainly includes C4 bump, μ-bump, and bumpless.
上述垂直互连的接触形式如下图所示
在这里插入图片描述

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本文为[tiaozhanzhe1900]所创,转载请带上原文链接,感谢
https://blog.csdn.net/tiaozhanzhe1900/article/details/126183018